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74LVC2G02-Q100

Dual 2-input NOR gate

The 74LVC2G02-Q100 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 1.65 V to 5.5 V

  • 5 V tolerant outputs for interfacing with 5 V logic

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC2G02DC-Q100Production1.65 - 5.5CMOS/LVTTL± 322.41502low-40~12520032.4110VSSOP8
74LVC2G02DP-Q100Production1.65 - 5.5CMOS/LVTTL± 322.41502low-40~12521018.8104TSSOP8

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC2G02DC-Q100
VSSOP8
(SOT765-1)
SOT765-1SOT765-1_125ActiveV0274LVC2G02DC-Q100H
( 9353 004 58125 )
74LVC2G02DP-Q100
TSSOP8
(SOT505-2)
SOT505-2SOT505-2_125ActiveV0274LVC2G02DP-Q100H
( 9353 004 59125 )

Environmental information

Type numberOrderable part numberChemical contentRoHSRHF-indicatorLeadfree conversion date
74LVC2G02DC-Q10074LVC2G02DC-Q100H74LVC2G02DC-Q100Always Pb-free
74LVC2G02DP-Q10074LVC2G02DP-Q100H74LVC2G02DP-Q100Always Pb-free
Quality and reliability disclaimer

Documentation (7)

File nameTitleTypeDate
74LVC2G02_Q100Dual 2-input NOR gateData sheet2023-08-15
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc2g0274LVC2G02 IBIS modelIBIS model2014-10-20
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyPackage information2022-06-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03

Support

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Models

File nameTitleTypeDate
lvc2g0274LVC2G02 IBIS modelIBIS model2014-10-20

Ordering, pricing & availability

Sample

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