74LVC2G38GS

Dual 2-input NAND gate; open drain

The 74LVC2G38 provides a 2-input NAND function.

The outputs of the 74LVC2G38 devices are open-drain and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant outputs for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM EIA/JESD22-A114F exceeds 2000 V
    • MM EIA/JESD22-A115-A exceeds 200 V
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Open-drain outputs
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC2G38GSProduction1.65 - 5.5CMOS/LVTTL322.11752low-40~1252699.7141XSON8

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC2G38GS
XSON8
(SOT1203)
SOT1203Reel 7" Q1/T1ActiveYB74LVC2G38GS,115
( 9352 923 85115 )

Quality

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74LVC2G38GS74LVC2G38GS,11574LVC2G38GSAlways Pb-free123.83.872.58E811
Quality and reliability disclaimer

Documentation (6)

File nameTitleTypeDate
74LVC2G38Dual 2-input NAND gate; open drainData sheet2017-03-17
AN11009Pin FMEA for LVC familyApplication note2011-02-04
AN212Package lead inductance considerations in high-speed applicationsApplication note2013-03-13
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
lvc2g3874LVC2G38 IBIS modelIBIS model2014-10-20
SOT1203plastic, extremely thin small outline package; 8 terminals; 0.55 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyOutline drawing2017-01-30

Support

Find answers to your design questions on this page. If available you can find information in our Nexperia Support Community or you can find Nexperia models and Design tools.

Models

File nameTitleTypeDate
lvc2g3874LVC2G38 IBIS modelIBIS model2014-10-20

Ordering

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