74LVC1G02GN

Single 2-input NOR gate

The 74LVC1G02 provides the single 2-input NOR function.

Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range from 1.65 V to 5.5 V
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G02GNProduction1.65 - 5.5CMOS/LVTTL+/- 322.11501low-40~12533823.5210XSON6

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC1G02GN
XSON6
(SOT1115)
SOT1115Reel 7" Q1/T1, Q3/T4ActiveVB74LVC1G02GN,132
( 9352 917 69132 )

Quality

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74LVC1G02GN74LVC1G02GN,13274LVC1G02GNAlways Pb-free123.83.872.58E811
Quality and reliability disclaimer

Documentation (8)

File nameTitleTypeDate
74LVC1G02Single 2-input NOR gateData sheet2017-03-17
AN10343MicroPak soldering informationApplication note2010-12-30
AN11009Pin FMEA for LVC familyApplication note2011-02-04
AN212Package lead inductance considerations in high-speed applicationsApplication note2013-03-13
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
lvc1g0274LVC1G02 IBIS modelIBIS model2014-10-20
SOT1115_132Reversed product orientation 12NC ending 132Packing2013-04-04
SOT1115plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 0.9 mm x 1 mm x 0.35 mm bodyOutline drawing2017-03-07

Support

Find answers to your design questions on this page. If available you can find information in our Nexperia Support Community or you can find Nexperia models and Design tools.

Models

File nameTitleTypeDate
lvc1g0274LVC1G02 IBIS modelIBIS model2014-10-20

Ordering

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