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IAN50010 - Low-cost DC-to-DC converter

This interactive application note details the design of a low cost DC-to-DC converter using a 555 timer IC, Nexperia switching transistors and power MOSFETs. Simulations and evaluation results are included.

Author: Rajesh Rajamony, Applications Engineer, Manchester

This interactive application note contains embedded Cloud based simulations to augment the text.

To open the embedded simulation, simply hover over the simulation image. Left click anywhere in the graphic area once the central play button changes in colour. This opens the schematic in the Cloud environment. See the interactive application note tutorial page for more details on how to use the simulations.

See accompanying application note AN50010.

Download AN50010

Introduction

DC-to-DC converters play a significant role in automotive systems. Fig. 1 shows some applications of DC-to-DC converters in different parts of an automotive system. Among the DC-to-DC converters, buck and boost converters are predominantly used to regulate the output voltage above or below the input voltage. Designing a cost-effective power converter is one of the main challenges, this application note discusses the discrete design of low-cost buck and boost converters. The design consists of the timer circuit, a gate driver circuit, voltage regulator circuit, and converter circuit. The timer, gate driver, and voltage regulator circuits are designed discretely in a cost-effective approach. The details of each of them are discussed in the following sections.

Figure 1. DC-to-DC converters in automotive systems

Figure 2. 555 timer functional block diagram

Timer circuit

The 555 timer is one of the popular precision timing devices which can produce pulses. The NE555 timer can operate in both monostable and astable modes. Fig. 2 shows the functional block diagram of the timer. The functional diagram consists of comparators, a voltage divider, a flip-flop  circuit, an output circuit, and a discharge unit. To reduce the cost, the schematic is designed by using minimal components. The schematic of the timer circuit is given in Fig. 3.

Comparing the functional and schematic illustrations (Fig. 2 and Fig. 3) will give a clear insight into each function of the timer circuit. The simulation of the timer circuit is presented in Simulation 1. The output of the timer circuit from the experimental setup is given in Fig. 4.

 

Figure 3. 555 timer schematic diagram

Simulation 1.

Simulation 1. 555 timer circuit simulation

Figure 4. 555 timer circuit output pulse waveform

Functional description of the 555 timer pins

In this section, short function descriptions of each timer pin are given, the reader is recommended to refer to Fig. 2 and Fig. 3. The standard NE555 timer has 8 pins:

  • Pin 1: Ground. The negative supply of the voltage divider, comparator, reset, and output units are connected to the ground pin. The negative voltages are measured with respect to the ground pin.

  • Pin 2: Trigger. The trigger pin is the negative input of the lower comparator. At the beginning of a time sequence, the trigger pin is used to set the latch to turn the output high. Triggering can be accomplished by taking the voltage level less than 1/3 of the supply voltage (VCC). In general, one-half of the control voltage will be appearing at this pin. To accomplish the level-sensitive action, a slow rate of change in waveform or pulses can be applied as a trigger source.

  • Pin 3: Output. The output pin of the timer is connected to a high current totem pole output stage, which consists of transistors Q12-Q14. Transistor Q13 provides a higher output voltage, less than the supply voltage level VCC. The transistor Q14 provides the ability to sink a substantial amount of current. Also, the low saturation voltage of Q14 permits a better noise margin for the driver during the operation of the current sink. 

  • Pin 4: Reset. This pin is used to reset the flip-flop. The reset input is an overriding function, which sets the output to a low state. The reset voltage depends on the operating voltage level of VCC. To prevent false resetting, the reset pin must be tied to the VCC, while it is not in use.

  • Pin 5: Control voltage. The control voltage pin is directly connected to the 2/3 VCC terminal of the voltage divider. This pin is directly connected to the inverting input of the upper comparator and indirectly connected to the non-inverting input of the lower comparator through a resistance. The main purpose of this pin is to control the voltage levels of the upper (threshold) and lower (trigger) comparators.

  • Pin 6: Threshold. This pin is connected to the non-inverting input of the upper comparator. It resets the flip-flop based on the threshold voltage level. The output sets to low when the threshold voltage is higher the 2/3 VCC. To achieve precise operation, a slow rate of change of voltage is applied to the threshold pin.

  • Pin 7: Discharge. The discharge pin is connected to the collector pin of the discharge transistor Q7. The base is connected to the flip-flop output and the emitter is connected to the ground. The conduction timing of the transistor is identical to the output stage. When the output is low, the transistor has low resistance to the ground, which turns ON the transistor and discharges the energy stored on the capacitor.

  • Pin 8: Supply. The supply pin is referred to as VCC, which is connected to the positive supply voltage of the device. The minimum and maximum power supply voltage of NE555 can be used between +4.5 V to +16 V. The specified operation ranges between +5 V to +15 V. The device will operate effectively over this range of voltages

Figure 5. Threshold and trigger comparators

Operation of the timer

The operation of the timer is explained using Fig. 3. The voltage divider of the timer consists of three resistors R7, R8, and R9, which all have equal resistance values. The reference voltage of the threshold and trigger comparators are supplied from the 2/3 VCC and 1/3 VCC of the divider. This can be noted in Fig. 6, the reference voltages are biasing the transistors Q3 and Q6.

The transistors Q1, Q2, and Q3 form the threshold comparator. The threshold comparator output is high if the threshold voltage is higher than the control voltage (2/3 VCC). Similarly, the transistors Q4, Q5, and Q6 have formed the trigger comparator. The collector current of Q1 and Q5 are the output of the comparators. In trigger comparator, Q4 acts as a common current source, which is used to make the current mirror along with Q11 and Q12. The trigger comparator output is high if the threshold voltage is lower than the voltage of 1/3 VCC.

Figure 7.

The comparator outputs are applied to the flip-flop circuit. The flip-flop circuit is formulated using transistors Q8-Q12. Fig. 6 shows the flip-flop circuit of the timer. When the threshold comparator is ON, the transistor Q9 is ON, which pulls the base of Q10 low and turns off Q10. This changes the flip-flop to an OFF state. When the trigger comparator is ON, the transistor Q8 is ON, which pulls the base of Q9 low and turns off Q9. This changes the flip-flop to an ON state. The output of the flip-flop is given to the output stage of the comparator.

Figure 6. Flip-flop circuit of the timer

Fig. 7 shows the output stage and discharge transistor of the timer. The output stage can be examined in two ways based on the flip-flop output. When the flip-flop output is low, Q13 is OFF and no bias current flows. The transistor Q14 follows the base voltage, which sets the output stage ON. When the flip-flop output is high, Q13 is ON, which turned ON the transistors Q7 and Q15. The resistors R15 and R17 are used to split the current from Q13 to drive the transistors Q7 and Q15. The transistor Q7 discharges the capacitor C1 and the transistor Q15 pulls the output stage OFF.

Figure 8. Gate driver for the buck converter

Driver circuit

The gate of the MOSFET drives using a high current and high switching speed driver circuit. The timer output is given to the input of the gate driver circuit. Fig. 8 shows the gate driver circuit buck converter (high-side driver). The drive consists of a pre-driver circuit, push-pull configuration, and bootstrap circuit. The pre-driver circuit consists of two NPN transistors Q16 and Q17. The output of the pre-driver circuit drives the push-pull configuration. Depending on the timer output, the pre-driver output is changed to lower or higher. When the timer output is low, Q16 is biased OFF and Q17 is biased ON through the resistance R22, which makes the node high. Hence, the transistor Q18 is biased ON and transistor Q17 is biased OFF, resulting in a high gate voltage. Similarly, when the timer output is high, the output node of the pre-driver is low, which makes the gate voltage low. The capacitor C2 maintains the required voltage of the driver.

Figure 9. Gate driver for the boost converter

Fig. 9 shows the gate driver circuit for the boost converter (low-side driver). The drive consists of a pre-driver circuit, and a push-pull configuration. The pre-driver circuit consists of two NPN transistors Q20 and Q21. The output of the pre-driver circuit drives the push-pull configuration. When the timer output is low, Q20 is biased OFF and Q21 is biased ON through the resistance R31, which makes the node high. Hence, the transistor Q22 is biased ON and transistor Q23 is biased OFF, resulting in a lower gate voltage.

Figure 10. Voltage regulator circuit

Voltage regulator circuit

The voltage regulator circuit is used to regulate the output voltage of the converter. Fig. 10 shows the voltage regulator circuit. The feedback loop control gain is generated by the parallel combination of R38 and R39. The value of R36 is selected to provide maximum bias current to Q24. The low-frequency components of the feedback signal are set by the value of C5. The shunt regulator can be configured to provide an arbitrary reference voltage. The output voltage can be set to any value using the external resistors R35 and R36. The output voltage VAK of the shunt regulator can be calculated as:

(Eq 1) 

Figure 11 a. Circuit diagram of the buck converter

Buck converter

The buck converter steps down the DC input voltage to output voltage. The operation of the converter depends on the stages of the MOSFET. Fig. 11 a shows the circuit diagram of the buck converter and Fig. 11 b and c  the operation in the ON and OFF states. Also, the converter operates in two modes which are the continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The details of the mode of operation are explained in the following sections.

Figure 11 b. Circuit diagram of the buck converter, S=ON

Buck converter operation in CCM

ON State: When the switch S is in the ON state, the current flows only through the inductor L to the output capacitor and the load resistor. Therefore, inductor current IL will increase and no current flows through the diode. The increase in current in the inductor during the ON state can be written as:

(Eq 2) 

where, Vin and Vout are the input and output voltage of the converter. D is the duty cycle and T is the total time.

Figure 11 c. Circuit diagram of the buck converter, S=OFF

OFF State: When the switch S is in the OFF state, the inductor current will decrease, which flows through the output capacitor, the load resistor, and the diode. The decrease in current in the inductor during the OFF state can be written as:

(Eq 3) 

The performance of the inductor current during CCM operation is given in Fig. 12. In CCM mode, the overall change in the inductor current is zero, which can be written as:

(Eq 4) 

Figure 12. Inductor current during the CCM operation

Substituting equations (2) and (3) in equation (4) and simplifying will give the output voltage with respect to the duty cycle:

(Eq 5) 

Buck converter operation in DCM

ON State: The ON state of the DCM operation is similar to the ON state of the CCM operation. The increase in current in the inductor during the ON state can be written as:

(Eq 6) 

OFF State: When the switch S is in the OFF state, the inductor current will decrease. The inductor current will reach to zero at D1 T before the end of one switching cycle. The decrease in current in the inductor during the OFF state can be written as:

(Eq 7) 

The performance of the inductor current during DCM operation is given in Fig. 13. The average inductor current is zero for one switching cycle, which can be written as:

(Eq 8) 

Substitute equations (6) and (7) in equation (8) and the simplifying will give the following expression:

(Eq 9) 

Figure 13. Inductor current during the DCM operation

The output current of the converter is equal to the average value of the inductor current, which can be written as:

(Eq 10) 

The inductor current is reached the peak value during the ON state of the switch (ΔIL,ON = IL,peak). Therefore, substituting equation (6) in equation (10) and simplifying gives the voltage conversion relationship of the buck converter:

(Eq 11) 

Simulation and experimental results of the buck converter

The complete simulation of the buck converter is presented in Simulation 2. The simulation is conducted in both steady and transient states. The transient simulation is performed by changing the input voltage from 10 V to 14 V and the load resistance from 5 Ω to 4 Ω. The reference voltage of the converter is set as 5 V. The simulation results ensured the converter regulated the output voltage with a fast response and without any overshoot or steady error.

Simulation 2

Simulation 2. Buck converter simulation

Prototype of DC-to-DC converters

A prototype PCB has been designed to evaluate the performance of the low-cost DC-to-DC converters. The Nexperia parts used to build the prototype are given in Table 1. The PCB is shown in Fig. 14.

Figure 14. Prototype PCB of a low-cost DC-to-DC converter
Table 1. Nexperia components used in the low-cost DC-to-DC converter
Component designator Nexperia parts
Timer
Q1, Q4, PMBT3906
Q2, Q3, PMP4501Y
Q5, Q6, Q11, Q12 PMP5201Y
Q7, Q8, Q9, Q10, Q13, Q14, Q15 PMBT2222
 
Gate driver
Q16, Q17, Q20, Q21 PMBT2222
Q18, Q19, Q22, Q23 BC846BPN
 
Voltage regulator
Q24 PMBT2222
Buck and Boost converter
Q45, Q49 BUK9V13-40H

Fig. 15 shows the gate voltage signal of the MOSFET. Then, the steady-state and transient experimental performance of the converter is verified. The steady-state conditions are, that the input voltage is 12 V, the reference output voltage is 5 V and the load resistance is 5 Ω. The steady-state input, output voltage and the output current of the buck converter is given in Fig. 16.

The transient experimental performance is verified by changing the input voltage from 10 V to 14 V and the load resistance from 5 Ω to 4 Ω. The transient state experimental results of the buck converter are given in Fig. 17. The steady and transient state experimental results confirmed the buck converter achieved the reference output voltage with a fast response and without any overshoot or steady error.

Figure 15. Buck converter gate voltage

Figure 16. Steady-state results of the buck converter

Figure 17 a) . Transient results of the buck converter -  input change

Figure  17 b). Transient results of the buck converter - load change

Figure 18 a) Circuit diagram of the boost converter

Boost converter

The boost converter steps up the DC input voltage to the required output voltage. Similar to the buck converter, the operation of the boost converter depends on the ON and OFF states of the MOSFET. Fig. 18 a) shows the circuit diagram of the boost converter and operation in the ON and OFF states. Depending on the inductor current, the operation of the converter is divided into two modes which are the CCM and DCM. The details of the mode of operation are explained in the following sections.

Figure 18 b) Circuit diagram of the boost converter, S=ON

Boost converter operation in CCM

ON State: When the switch S is in the ON state, the inductor current will increase and no current flows through the diode. The increase in current in the inductor during the ON state can be written as:

(Eq 12) 

Figure 18 c) Circuit diagram of the boost converter, S=OFF

OFF State: When the switch S is in the OFF state, the inductor current will flow through the diode to the output capacitor and the load resistor. The decrease in current in the inductor during the OFF state can be written as:

(Eq 13) 

In CCM mode, the overall change in the inductor current is zero, which can be written as:

(Eq 14) 

Substitute equations (12) and (13) in equation (14) and the simplifying will give the output voltage with respect to the duty cycle:

(Eq 15) 

Boost converter operation in DCM

ON State: In the ON state, the inductor current increases to the peak value. The increase in current in the inductor during the ON state can be written as:

(16) 

OFF State: When the switch S is in the OFF state, the inductor current decreases and will reach to zero at D1 T before the end of one cycle. The decrease in current in the inductor during the OFF state can be written as:

(17) 

The sum of the change in the inductor current over a period of time is equal to zero, which can be written as:

(18) 

Substituting equations (16) and (17) in equation (18) and the simplifying will give the following expression:

(19) 

The output current of the converter is equal to the average value of the diode current, which can be written as:

(20) 

During the ON state of the switch, the inductor current reaches the peak value (ΔIL,ON =IL,peak). Therefore, substituting equation (16) in equation (20) and simplifying, the voltage conversion relationship of the boost converter can be derived:

(21)

 

Simulation and experimental results of the boost converter

The complete simulation of the boost converter is presented in Simulation 3. The simulation is conducted in both steady and transient states. The transient simulation is performed by changing the input voltage from 10 V to 12 V and the load resistance from 180 Ω to 80 Ω. The reference output voltage of the converter is set as 30 V. The simulation results are ensured the boost converter regulated the output voltage with a fast response and without any overshoot or steady error.

Figure 19. Boost converter gate voltage

Figure 20. Steady-state results of the boost converter

Figure 21 a). Transient results of the boost converter, input change

Figure 21 b) Transient results of the boost converter, load change

Simulation 3

The complete simulation of the boost converter is presented in Simulation 3. The simulation is conducted in both steady and transient states. The transient simulation is performed by changing the input voltage from 10 V to 12 V and the load resistance from 180 Ω to 80 Ω. The reference output voltage of the converter is set as 30 V. The simulation results are ensured the boost converter regulated the output voltage with a fast response and without any overshoot or steady error.

Simulation 3: Boost converter simulation

Conclusion

In this interactive application note, the design of a low-cost buck and boost converter is presented using the Nexperia parts. The performance of the design has been verified in both simulation and experimentally. The performance validation is conducted using steady and transient analysis. The steady and transient results are confirmed the converters achieved the reference output voltage with a fast response time and without any overshoot or steady error.

Page last updated 08 August 2022.