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NPIC6C595-Q100 NRND

Power logic 8-bit shift register; open-drain outputs

The NPIC6C595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset input (MR). A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input and to the Q7S output on a LOW-to-HIGH transition of the SHCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. Data in the storage register drives the gate of the output extended-drain NMOS transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs.

Integrated voltage clamps in the outputs provide protection against inductive transients making the device suitable for power driver applications such as relay, solenoids and other low-current or medium-voltage loads.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Not recommended for new designs (NRND).

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +125 °C

  • Low RDSon

  • Eight Power EDNMOS transistor outputs of 100 mA continuous current

  • 250 mA current limit capability

  • Output clamping voltage 33 V

  • 30 mJ avalanche energy capability

  • All registers cleared with single input

  • Low power consumption

  • ESD protection:

    • HBM AEC-Q100-002 revision D exceeds 2500 V

    • CDM AEC-Q100-011 revision B exceeds 1000 V

  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

Applications

  • LED sign

  • Graphic status panel

  • Fault status indicator

Documentation (5)

File nameTitleTypeDate
NPIC6C595_Q100Power logic 8-bit shift register; open-drain outputsData sheet2020-06-10
AN11537Pin FMEA for NPIC FamilyApplication note2019-10-07
npic6c595NPIC6C595 IBIS modelIBIS model2016-05-29
Nexperia_document_leaflet_Logic_NPIC_ShiftRegisters_201906NPIC Logic Shift RegistersLeaflet2019-07-12
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10

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Models

File nameTitleTypeDate
npic6c595NPIC6C595 IBIS modelIBIS model2016-05-29