74AUP2G240

Low-power dual inverting buffer/line driver; 3-state

The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH.

Features and benefits

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low-noise overshoot and undershoot < 10 % of V_CC
Input-disable feature allows floating input conditions
I_OFF circuitry provides partial Power-down mode operation
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	f_max (MHz)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	R_th(j-c) (K/W)	Package name
74AUP2G240DC	Production	0.8 - 3.6	CMOS	± 1.9	70	2	ultra low	-40~125	203	113	VSSOP8
74AUP2G240GN	Production	0.8 - 3.6	CMOS	± 1.9	70	2	ultra low	-40~125	238	148	XSON8
74AUP2G240GS	Production	0.8 - 3.6	CMOS	± 1.9	70	2	ultra low	-40~125	276	146	XSON8
74AUP2G240GT	Production	0.8 - 3.6	CMOS	± 1.9	70	2	ultra low	-40~125	327	157	XSON8

Package

Type number	Package	Package information	Reflow-/Wave soldering	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AUP2G240DC	VSSOP8 (SOT765-1)	SOT765-1		SOT765-1_125	Active	p40	74AUP2G240DC,125 ( 9352 807 36125 )
74AUP2G240GN	XSON8 (SOT1116)	SOT1116	REFLOW_BG-BD-1	SOT1116_115	Active	p2	74AUP2G240GN,115 ( 9352 922 24115 )
74AUP2G240GS	XSON8 (SOT1203)	SOT1203	REFLOW_BG-BD-1	SOT1203_115	Active	p2	74AUP2G240GS,115 ( 9352 927 84115 )
74AUP2G240GT	XSON8 (SOT833-1)	SOT833-1		SOT833-1_115	Active	p40	74AUP2G240GT,115 ( 9352 807 37115 )

Environmental information

Type number	Orderable part number	Chemical content	Leadfree conversion date
74AUP2G240DC	74AUP2G240DC,125	74AUP2G240DC	Always Pb-free
74AUP2G240GN	74AUP2G240GN,115	74AUP2G240GN	Always Pb-free
74AUP2G240GS	74AUP2G240GS,115	74AUP2G240GS	Always Pb-free
74AUP2G240GT	74AUP2G240GT,115	74AUP2G240GT	Always Pb-free

Quality and reliability disclaimer

Documentation (15)

File name	Title	Type	Date
74AUP2G240	Low-power dual inverting buffer/line driver; 3-state	Data sheet	2023-07-27
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup2g240	aup2g240 IBIS model	IBIS model	2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10
MAR_SOT1203	MAR_SOT1203 Topmark	Top marking	2013-06-03
SOT1203	plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body	Package information	2022-06-03
REFLOW_BG-BD-1	Reflow soldering profile	Reflow soldering	2021-04-06
MAR_SOT833	MAR_SOT833 Topmark	Top marking	2013-06-03
SOT833-1	plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body	Package information	2022-06-03
SOT765-1	plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body	Package information	2022-06-03
MAR_SOT1116	MAR_SOT1116 Topmark	Top marking	2013-06-03
SOT1116	plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm body	Package information	2022-06-02
REFLOW_BG-BD-1	Reflow soldering profile	Reflow soldering	2021-04-06

Support

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Models

File name	Title	Type	Date
aup2g240	aup2g240 IBIS model	IBIS model	2013-04-07

Ordering, pricing & availability

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