74LVC2G34-Q100

Dual buffer gate

The 74LVC2G34-Q100 is a dual buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (V_CC = 3.0 V)
CMOS low power dissipation
I_OFF provides partial Power-down mode operation
Direct interface with TTL levels
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74LVC2G34GM-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 32	2.2	175	2	low	-40~125	290	6.5	145	XSON6
74LVC2G34GV-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 32	2.2	175	2	low	-40~125	231	39.1	145	TSOP6
74LVC2G34GW-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 32	2.2	175	2	low	-40~125	264	38.4	153	TSSOP6

Package

Type number	Package	Package information	Reflow-/Wave soldering	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74LVC2G34GM-Q100	XSON6 (SOT886)	SOT886	REFLOW_BG-BD-1	SOT886_125	Active	YA	74LVC2G34GM-Q100,1 ( 9352 990 49125 )
74LVC2G34GV-Q100	TSOP6 (SOT457)	SOT457	REFLOW_BG-BD-1 WAVE_BG-BD-1	SOT457_125	Active	Y34	74LVC2G34GV-Q100,1 ( 9352 990 51125 )
74LVC2G34GW-Q100	TSSOP6 (SOT363-2)	SOT363-2		SOT363-2_125	Active	YA	74LVC2G34GW-Q100,1 ( 9352 990 52125 )

Environmental information

Type number	Orderable part number	Chemical content	Leadfree conversion date
74LVC2G34GM-Q100	74LVC2G34GM-Q100,1	74LVC2G34GM-Q100	Always Pb-free
74LVC2G34GV-Q100	74LVC2G34GV-Q100,1	74LVC2G34GV-Q100	Always Pb-free
74LVC2G34GW-Q100	74LVC2G34GW-Q100,1	74LVC2G34GW-Q100	Always Pb-free

Quality and reliability disclaimer

Documentation (14)

File name	Title	Type	Date
74LVC2G34_Q100	Dual buffer gate	Data sheet	2023-08-22
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11009	Pin FMEA for LVC family	Application note	2019-01-09
lvc2g34	74LVC2G34 IBIS model	IBIS model	2015-09-06
Nexperia_document_leaflet_Logic_X2SON_packages_062018	X2SON ultra-small 4, 5, 6 & 8-pin leadless packages	Leaflet	2018-06-05
Nexperia_document_leaflet_Logic_Automotive_MicroPak_solutions_201904	Automotive logic in MicroPak leadless packages	Leaflet	2019-04-18
SOT363-2	plastic thin shrink small outline package; 6 leads; body width 1.25 mm	Package information	2022-11-21
MAR_SOT886	MAR_SOT886 Topmark	Top marking	2013-06-03
SOT886	plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body	Package information	2022-06-01
REFLOW_BG-BD-1	Reflow soldering profile	Reflow soldering	2021-04-06
MAR_SOT457	MAR_SOT457 Topmark	Top marking	2013-06-03
WAVE_BG-BD-1	Wave soldering profile	Wave soldering	2021-09-08
SOT457	plastic, surface-mounted package (SC-74; TSOP6); 6 leads	Package information	2023-03-03
REFLOW_BG-BD-1	Reflow soldering profile	Reflow soldering	2021-04-06

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Models

File name	Title	Type	Date
lvc2g34	74LVC2G34 IBIS model	IBIS model	2015-09-06

Ordering, pricing & availability

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