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74AXP2T3407 NRND

Dual supply single buffer and single buffer with open-drain

The 74AXP2T3407 is a dual supply single buffer and a single buffer with open-drain output. It features two input pins (nA), an output pin (1Y) and an open-drain output pin (2Y) and dual supply pins (VCCI and VCCO). The inputs are referenced to VCCI and the output is referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between 0.7 V and 2.75 V and VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This feature allows voltage level translation.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Not recommended for new designs (NRND).

Features and benefits

  • Wide supply voltage range:

    • VCCI: 0.7 V to 2.75 V

    • VCCO: 1.2 V to 5.5 V

  • Low input capacitance; CI = 0.6 pF (typical)

  • Low output capacitance; CO = 1.8 pF (typical) for 1Y

  • Low output capacitance; CO = 1.3 pF (typical) for 2Y

  • Low dynamic power consumption; CPD = 0.4 pF at VCCI = 1.2 V (typical)

  • Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)

  • Low static power consumption; ICCI = 0.5 μA (85 °C maximum)

  • Low static power consumption; ICCO = 1.8 μA (85 °C maximum)

  • High noise immunity

  • Complies with JEDEC standard:

    • JESD8-12A.01 (1.1 V to 1.3 V; nA inputs)

    • JESD8-11A.01 (1.4 V to 1.6 V)

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A.01 (2.3 V to 2.7 V)

    • JESD8-C (2.7 V to 3.6 V; nY outputs)

    • JESD12-6 (4.5 V to 5.5 V; nY outputs)

  • ESD protection:

    • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV

    • CDM JESD22-C101E exceeds 1000 V

  • Latch-up performance exceeds 100 mA per JESD78D Class II

  • Inputs accept voltages up to 2.75 V

  • Low noise overshoot and undershoot < 10% of VCCO

  • IOFF circuitry provides partial power-down mode operation

  • Multiple package options

  • Specified from -40 °C to +85 °C

Documentation (6)

File nameTitleTypeDate
74AXP2T3407Dual supply single buffer and single buffer with open-drainData sheet2017-03-17
AN90029Pin FMEA for AXPnT familyApplication note2021-07-13
Nexperia_document_guide_Logic_translatorsNexperia Logic TranslatorsBrochure2021-04-12
axp2t340774AXP2T3407 IBIS modelIBIS model2016-03-02
Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904AXP – Extremely low-power logic technology portfolioLeaflet2019-04-05
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10

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Models

File nameTitleTypeDate
axp2t340774AXP2T3407 IBIS modelIBIS model2016-03-02