74AVC1T1022

1-to-4 fan-out buffer

The 74AVC1T1022 is a translating 1-to-4 fan-out buffer suitable for use in clock distribution. It has dual supplies (V_CC(A) and V_CC(B)) for voltage translation. It also has a data input (A), four data outputs (1Yn and 2Yn) and an output enable input (OE). V_CC(A) and V_CC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V. It makes the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The levels of A, OE and 1Yn are referenced to V_CC(A), outputs 2Yn are referenced to V_CC(B). This supply configuration ensures that two of the fanned out signals can be used in level shifting. A HIGH on OE causes all outputs to be pulled LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors and enables all outputs.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

The I_OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down.

Features and benefits

Wide supply voltage range:
- V_CC(A): 0.8 V to 3.6 V
- V_CC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8 kV
- CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
- 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
- 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
- 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
- 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
- 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
- 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
- Latch-up performance exceeds 100 mA per JESD 78 Class II
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
- Multiple package options
- Inputs accept voltages up to 3.6 V

Parametrics

Type number	Product status	V_CC(A) (V)	V_CC(B) (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AVC1T1022DP	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	4.0	1	very low	-40~125	186	22.5	94.6	TSSOP10
74AVC1T1022GU	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	4.0	1	very low	-40~125	236	17.7	137	XQFN10

Package

Type number	Package	Package information	Reflow-/Wave soldering	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AVC1T1022DP	TSSOP10 (SOT552-1)	SOT552-1	SSOP-TSSOP-VSO-WAVE	SOT552-1_118	Active	B2	74AVC1T1022DPJ ( 9353 058 31118 )
74AVC1T1022GU	XQFN10 (SOT1160-1)	SOT1160-1		SOT1160-1_115	Active	B2	74AVC1T1022GUX ( 9353 058 32115 )

Environmental information

Type number	Orderable part number	Chemical content	RoHS	RHF-indicator	Leadfree conversion date
74AVC1T1022DP	74AVC1T1022DPJ	74AVC1T1022DP			Always Pb-free
74AVC1T1022GU	74AVC1T1022GUX	74AVC1T1022GU			Always Pb-free

Quality and reliability disclaimer

Documentation (7)

File name	Title	Type	Date
74AVC1T1022	1-to-4 fan-out buffer	Data sheet	2017-03-16
Nexperia_document_guide_Logic_translators	Nexperia Logic Translators	Brochure	2021-04-12
avc1t1022	74AVC1T1022 IBIS model	IBIS model	2015-10-25
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10
SSOP-TSSOP-VSO-WAVE	Footprint for wave soldering	Wave soldering	2009-10-08
SOT552-1	plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm body	Package information	2022-06-07
SOT1160-1	plastic, leadless extremely thin quad flat package; 10 terminals; 0.4 mm pitch; 1.4 mm x 1.8 mm x 0.5 mm body	Package information	2022-06-07

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Models

File name	Title	Type	Date
avc1t1022	74AVC1T1022 IBIS model	IBIS model	2015-10-25

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