74LVC8T595

Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state

The 74LVC8T595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register.

VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins MR, SHCP, STCP, OE, DS and Q7S are referenced to VCC(A) and pins Qn are referenced to VCC(B).

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when VCC(A) is at GND level, the Qn outputs are in the high-impedance OFF-state.

Features

  • • Wide supply voltage range:
    • VCC(A): 1.1 V to 5.5 V
    • VCC(B): 1.1 V to 5.5 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12A (1.1 V to 1.3 V)
    • JESD8-11A (1.4 V to 1.6 V)
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (3.0 V to 3.6 V)
    • JESD12-6 (4.5 V to 5.5 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4000V
    • CDM JESD22-C101E exceeds 1000 V
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • ±24 mA output drive (VCC(A) = VCC(B) = 3.0 V)
  • Inputs accept voltages up to 5.5 V
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC8T595BQProduction1.1 - 5.51.1 - 5.5CMOS/LVTTL± 244.18low-40~125767.347DHVQFN20
74LVC8T595PWProduction1.1 - 5.51.1 - 5.5CMOS/LVTTL± 244.18low-40~1251004.343TSSOP20

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC8T595BQ
DHVQFN20
(SOT764-1)
SOT764-1Reel 7" Q1/T1ActiveStandard Marking74LVC8T595BQX
( 9353 091 43115 )
74LVC8T595PW
TSSOP20
(SOT360-1)
SOT360-1SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1ActiveStandard Marking74LVC8T595PWJ
( 9353 091 44118 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74LVC8T595BQ74LVC8T595BQX74LVC8T595BQweek 25, 201911
74LVC8T595PW74LVC8T595PWJ74LVC8T595PWweek 25, 201911
Quality and reliability disclaimer

Documentation (8)

File nameTitleTypeDate
74LVC8T595Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-stateData sheet2017-07-27
Nexperia_document_guide_Logic_translators_201711Nexperia Logic TranslatorsBrochure2017-12-05
Nexperia_document_leaflet_Logic_74LVC8T595_201711Voltage-translating Shift Register for Modular DesignsLeaflet2017-11-29
SOT764-1_115DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering code (12NC) ending 115Packing2013-04-23
SOT764-1plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm bodyOutline drawing2018-11-14
SOT360-1_118TSSOP20; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-15
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT360-1plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm bodyOutline drawing2018-10-18

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