74LVC16374ADL NRND

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.

When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

Not recommended for new designs (NRND), click here for the alternative product.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74LVC16374ADL 74LVC16374ADL,118 935235180118 SOT370-1 Order product
74LVC16374ADL 74LVC16374ADL,112 935235180112 SOT370-1 Order product

Features

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Multibyte flow-through standard pin-out architecture
  • Low inductance multiple supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold (74LVCH16374A only)
  • High-impedance outputs when VCC = 0 V
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-B exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74LVC16374ADL
NRND
Not for design in1.2 - 3.6CMOS/LVTTL+/- 243.8150low-40~1258825.0SSOP48

Package

Type numberOrderable part number, (Ordering code (12NC))StatusMarkingPackageOutline versionReflow-/Wave solderingPacking
74LVC16374ADL
NRND
74LVC16374ADL,118
( 9352 351 80118 )
ActiveLVC16374A
SSOP48
(SOT370-1)
SOT370-1SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1
74LVC16374ADL,112
( 9352 351 80112 )
ActiveLVC16374ABulk Pack

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFMSLMSL leadfree
74LVC16374ADL
NRND
74LVC16374ADL,118Not available11
74LVC16374ADL
NRND
74LVC16374ADL,112Not available11
Quality and reliability disclaimer

Documentation (7)

File nameTitleTypeDate
74LVC_LVCH16374A16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-stateData sheet2018-11-20
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc16374alvc16374a IBIS modelIBIS model2013-04-07
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SSOP-TSSOP-VSO-REFLOWFootprint for reflow solderingReflow soldering2009-10-08
SOT370-1_118Standard product orientation 12NC ending 118Packing2013-04-19
SOT370-1plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm bodyOutline drawing2018-10-18

Support

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Models

File nameTitleTypeDate
lvc16374alvc16374a IBIS modelIBIS model2013-04-07

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74LVC16374ADL74LVC16374ADL,118935235180118Reel 13" Q1/T1Order product
74LVC16374ADL74LVC16374ADL,112935235180112Bulk PackOrder product

Sample

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Sample orders normally take 2-4 days for delivery.

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