- Supports up to 208 MHz clock rate
- Feedback channel for clock synchronization
- SD 3.0 specification-compliant voltage translation to support SDR104, SDR50, DDR50, SDR25, SDR12, high-speed and default-speed modes
- 100 mA low dropout voltage regulator to supply the card-side I/Os
- Low power consumption by push-pull output stage with break-before-make architecture
- Integrated pull-up and pull-down resistors: no external resistors required
- Integrated EMI filters suppress higher harmonics of digital I/Os
- Integrated 8 kV ESD protection according to IEC 61000-4-2, level 4 on card side
- Level shifting buffers keep ESD stress away from the host (zero-clamping concept)
- 25-ball WLCSP; pitch 0.4 mm
- Mobile handsets
- Digital cameras
- Tablet PCs
- Laptop computers
- SD, MMC or microSD card readers
|Type number||Package version||Package name||Size (mm)|
|IP4856CX25||WLCSP25_5X5||WLCSP25||2 x 2 x 0.5|
|IP4856CX25_C||SD 3.0-compliant memory card integrated dual voltage level translator with EMI filter and ESD protection||Data sheet||2017-03-11|
|nexperia_document_leaflet_WLCSP_201803||Small-signal MOSFETs in WLCSP - Smallest size - lowest RDS(on)||Leaflet||2018-04-25|
|WLCSP25_5X5||wafer level chip-size package; 25 bumps; 0.4 mm pitch; 2 x 2 x 0.5 mm body||Outline drawing||2017-06-07|
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