- Supply voltage range from 2.3 V to 3.6 V
- High noise immunity
- Complies with JEDEC standard:
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
- 5 Ω switch connection between two ports
- Rail to rail switching on data I/O ports
- CMOS low power consumption
- Latch-up performance meets requirements of JESD78 Class I
- IOFF circuitry provides partial power down mode operation
- Multiple package options
- Specified from -40 C° to +85 °C and -40 °C to +125 °C
|Type number||Product status||VCC (V)||VPASS (V)||Logic switching levels||RON (Ohm)||f(-3dB) (MHz)||No of bits||tpd (ns)||Power dissipation considerations||Tamb (Cel)||Rth(j-a) (K/W)||Ψth(j-top) (K/W)||Rth(j-c) (K/W)||Package name|
|74CBTLV1G125GW||Production||2.3 - 3.6||3.3||CMOS / LVTTL||7||400||1||0.2||very Low||-40~125||300||71.7||171||TSSOP5|
|74CBTLV1G125||Single bus switch||Data sheet||2017-03-17|
|AN10161||PicoGate Logic footprints||Application note||2002-10-29|
|75017511||Voltage translation: How to manage mixed-voltage designs with NXP level translators||Brochure||2014-05-19|
|SOT353-1_125||TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code (12NC) ending 125||Packing||2017-11-16|
|SOT353-1||plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body||Outline drawing||2017-01-30|
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