74AVC2T45DP

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual-supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In Suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.

Features

  • Wide supply voltage range:
    • VCC(A): 0.8 V to 3.6 V
    • VCC(B): 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3B exceeds 8000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101C exceeds 1000 V
  • Maximum data rates:
    • 500 Mbit/s (1.8 V to 3.3 V translation)
    • 320 Mbit/s (<1.8 V to 3.3 V translation)
    • 320 Mbit/s (translate to 2.5 V or 1.8 V)
    • 280 Mbit/s (translate to 1.5 V)
    • 240 Mbit/s (translate to 1.2 V)
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from –40 ℃ to +85 ℃ and –40 ℃ to +125 ℃

Target applications

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AVC2T45DPProduction0.8 - 3.60.8 - 3.6CMOS/LVTTL+/- 122.12very low-40~12521720.6106TSSOP8

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AVC2T45DP
TSSOP8
(SOT505-2)
SOT505-2Reel 7" Q3/T4, ReverseActiveB4574AVC2T45DP,125
( 9352 867 74125 )

Quality

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AVC2T45DP74AVC2T45DP,12574AVC2T45DPAlways Pb-free11
Quality and reliability disclaimer

Documentation (9)

File nameTitleTypeDate
74AVC2T45Dual-bit, dual-supply voltage level translator/transceiver; 3-stateData sheet2013-02-08
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN252Live Insertion Aspects of Philips Logic FamiliesApplication note2013-03-13
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
75017511Voltage translation: How to manage mixed-voltage designs with NXP level translatorsBrochure2014-05-19
avc2t4574AVC2T45 IBIS modelIBIS model2014-10-19
75017085Application guide: Flat-panel TV setsLine card2012-03-12
75017090Application guide; Portable devices and mobile handsetsSelection guide2012-03-12
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyOutline drawing2017-01-30

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Models

File nameTitleTypeDate
avc2t4574AVC2T45 IBIS modelIBIS model2014-10-19

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