74AXP1T57 NRND

Dual supply configurable multiple function gate

The 74AXP1T57 is a dual supply configurable multiple function gate with Schmitt-trigger inputs. It features three inputs (A, B and C), an output (Y) and dual supply pins (V_CCI and V_CCO). The inputs are referenced to V_CCI and the output is referenced to V_CCO. All inputs can be connected directly to V_CCI or GND. V_CCI can be supplied at any voltage between 0.7 V and 2.75 V and V_CCO can be supplied at any voltage between 1.2 V and 5.5 V. This feature allows voltage level translation. The 74AXP1T57 can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer.

This device ensures very low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Not recommended for new designs (NRND).

Features and benefits

Wide supply voltage range:
- V_CCI: 0.7 V to 2.75 V
- V_CCO: 1.2 V to 5.5 V
Low input capacitance; C_I = 0.6 pF (typical)
Low output capacitance; C_O = 1.8 pF (typical)
Low dynamic power consumption; C_PD = 0.6 pF at V_CCI = 1.2 V (typical)
Low dynamic power consumption; C_PD = 7.1 pF at V_CCO = 3.3 V (typical)
Low static power consumption; I_CCI = 0.5 µA (85 °C maximum)
Low static power consumption; I_CCO = 1.8 µA (85 °C maximum)
High noise immunity
Complies with JEDEC standard:
- JESD8-12A.01 (1.1 V to 1.3 V; A, B, C inputs)
- JESD8-11A.01 (1.4 V to 1.6 V)
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A.01 (2.3 V to 2.7 V)
- JESD8-C (2.7 V to 3.6 V; Y output)
- JESD12-6 (4.5 V to 5.5 V; Y output)
ESD protection:
- HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
- CDM JESD22-C101E exceeds 1 kV
Latch-up performance exceeds 100 mA per JESD78D Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10% of V_CCO
I_OFF circuitry provides partial power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Documentation (7)

File name	Title	Type	Date
74AXP1T57	Dual supply configurable multiple function gate	Data sheet	2022-06-17
AN90029	Pin FMEA for AXPnT family	Application note	2021-07-13
Nexperia_document_guide_Logic_translators	Nexperia Logic Translators	Brochure	2021-04-12
axp1t57	74AXP1T57 IBIS model	IBIS model	2016-03-01
Nexperia_document_leaflet_Logic_X2SON_packages_062018	X2SON ultra-small 4, 5, 6 & 8-pin leadless packages	Leaflet	2018-06-05
Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904	AXP – Extremely low-power logic technology portfolio	Leaflet	2019-04-05
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10

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Models

File name	Title	Type	Date
axp1t57	74AXP1T57 IBIS model	IBIS model	2016-03-01