We are pleased to invite you to the fourth session “Impact of various inductances on system-level ESD and pitfalls in transmission line pulse measurements” of our ESD expert series. The duration is one hour for two presentations, plus time for questions.

The same sessions will run on October 7th and 12th, 2021 to support different time zones. Clicking on the below links will offer you the option to show the event in your time zone.

Register for October 7th, 5pm CEST Register for October 12th, 10am CEST

If you desire more fundamental knowledge of system-level ESD protection, are a Design Engineer, EMC Engineer, Validation Test Engineer working with ESD Module / System Test Standards and Test Equipment, Engineer running Certified EMC Test Facilities or ESD and RF simulation specialist - this Workshop is right for you!

After registering, you will receive a confirmation email containing information about joining the webinar. Mind, that number of seats in the sessions is limited - first come first served.

The training portal will be open 15 minutes before the training starts. Please sign up in advance.

Seminars will run via GoToWebinar conferencing system. If you were not using it earlier, we recommend you to plan at least 5 minutes extra for plug-in/app installation at your device.

Agenda and speakers


  • Impact of parasitic and EMI filter inductances on system-level ESD protection in high-speed data lines                                       

This presentation will provide a broad overview on how specific inductances improve system-level ESD robustness in high-speed data lines. Those inductances are either intrinsic PCB parasitics of microstrip lines or added to the system via EMI filters, i.e. Common Mode Chokes (CMC). The influence of the relatively small parasitic inductances <10nH is analyzed by mixed-mode TCAD-device simulation. Furthermore, the system ESD impact of different CMC inductances ranging from 30nH to 100uH for filters with and without ferrites are analyzed by TLP, vf-TLP, and ESD measurements. The presented results are relevant for different high-speed applications such as USB4.x, HDMI2.0, and automotive multi-Gigabit Ethernet.

Speaker: Markus Mergens, Nexperia, Hamburg, Germany


  • Pitfalls of TLP, VF-TLP and HMM for ultra-high-current analysis of ESD discretes

​​​​​​​In this presentation the author will introduce briefly the advantages of the Transmission Line Pulse (TLP) generator for the characterization of semiconductor devices in the time domain. Pitfalls of the standard TLP and very-fast (VF) TLP setup will be explained, such as erroneous pulse reflections, misleading probe contact resistance, time artifacts and blind regions as well as the accuracy of transient trigger peak analysis for ESD protection devices.The human metal model (HMM) will be discussed versus application of the VF-TLP/TLP methods. Conclusions will round up the key statements.

Speaker: Werner Simbürger, HPPI GmbH, Munich, Germany