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74ABT16841ADL

74ABT16841ADL End of life

20-bit bus interface latch (3-State)

The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity.

The 74ABT16841A consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE HIGH-to-LOW transition, the data that meets the set-up and hold time is latched.

Data appears on the bus when the Output Enable (nOE) is LOW. When nOE is HIGH the output is in the high-impedance state.

  • Product details
  • Documentation
  • Support
  • Interactive data sheet

Product details

Features and benefits

  • High speed parallel latches
  • Live insertion/extraction permitted
  • Extra data width for wide address/data paths or buses carrying parity
  • Power-up 3-State
  • Power-up reset
  • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
  • Output capability: +64 mA / ?32 mA
  • Latch-up protection exceeds 500 mA per Jedec Std 17
  • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

Applications

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More information

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Longevity

The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.

Interactive data sheet

How does it work?

The interactive data sheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive data sheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

Interactive data sheet