74LVC573ABQ

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Alternatives

74LVC573ABQ-Q100

Octal D-type transparent latch with 5 V tolerantinputs/outputs; 3-state Automotive qualified

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

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Features and benefits

Wide supply voltage range from 1.2 to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
I_OFF circuitry provides partial Power-down mode operation
High-impedance when V_CC = 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-B exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74LVC573ABQ	Production	1.2 - 3.6	TTL	± 24	3.4	low	-40~125	79	9.5	50	DHVQFN20

Package

Type number	Orderable part number, (Ordering code (12NC))	Status	Marking	Package	Package information	Reflow-/Wave soldering	Packing
74LVC573ABQ	74LVC573ABQ,115 ( 9352 735 07115 )	Active	LVC573A	DHVQFN20 (SOT764-1)	SOT764-1		Reel 7” Q1/T1 or Q2/T3

Environmental information

Type number	Orderable part number	Chemical content	RoHS	RHF-indicator
74LVC573ABQ	74LVC573ABQ,115	74LVC573ABQ

Quality and reliability disclaimer

Series

74LVC573A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

Documentation (6)

File name	Title	Type	Date
74LVC573A	Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state	Data sheet	2021-08-27
AN263	Power considerations when using CMOS and BiCMOS logic devices	Application note	2023-02-07
AN11009	Pin FMEA for LVC family	Application note	2019-01-09
lvc573a	lvc573a IBIS model	IBIS model	2013-04-07
74LVC573ABQ_Nexperia_Product_Reliability	74LVC573ABQ Nexperia Product Reliability	Quality document	2022-05-04
lvc	lvc Spice model	SPICE model	2013-05-06

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Models

File name	Title	Type	Date
lvc573a	lvc573a IBIS model	IBIS model	2013-04-07
lvc	lvc Spice model	SPICE model	2013-05-06

Ordering, pricing & availability

Type number	Orderable part number	Ordering code (12NC)	Packing	Packing quantity	Buy online
74LVC573ABQ	74LVC573ABQ,115	935273507115	Reel 7” Q1/T1 or Q2/T3	-	Order product

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