Register once, drag and drop ECAD models into your CAD tool and speed up your design.

Click here for more information

74AUP1G97UK NRND ECAD models PCB Symbol, Footprint & ECAD Model

Low-power configurable multiple function gate

The 74AUP1G97 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

Not recommended for new designs (NRND), click here for the alternative product.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • ESD protection:
    • HBM JESD22-A114F exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (°C)Package name
74AUP1G97UK
NRND
Not for design in0.8 - 3.6n.a.CMOS± 1.98.7701ultra low-40~125WLCSP6

Documentation (4)

File nameTitleTypeDate
74AUP1G97Low-power configurable multiple function gateData sheet2017-04-14
aup1g97aup1g97 IBIS modelIBIS model2015-09-06
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
SOT1454-1wafer level chip-scale package, 6 bumpsOutline drawing2018-10-18

Support

If you are in need of design/technical support, let us know and fill in the answer form, we'll get back to you shortly.

Models

File nameTitleTypeDate
aup1g97aup1g97 IBIS modelIBIS model2015-09-06