I2C voltage translation and repeaters

Today's electronic systems are significantly more complex. This is clearly visible with the increased complexity found in I2C-bus communications. For I2C master/slave interfaces there is a trend towards higher bus speed (standard, Fast-mode, FM+), with multi-voltage bus branches common and a need for support of clock-stretching. Regardless of the complexity, Nexperia can offer a solution to meet your needs.

Block diagram

Design considerations

  • Potential for high capacitive bus load, handling FM+ speed (1 MHz)
  • I2C master and slaves operating from 0.8 V to 5 V
  • Need to split or separate I2C branches
  • Support for clock-stretching

Logic Application Handbook

Download Nexperia’s Logic Design Engineer’s Guide and get a better understanding of Logic products, their features and properties, timing and interfacing aspects as well as get an overview of application insights.

Download it now

Selection Guide 2021

The 2021 edition of the Nexperia Selection Guide presents all our Discrete, Logic and MOSFET devices in one single document to give you a complete overview of our portfolio, making it easier for you to find the right product for your design.

Download it now