Features and benefits
- 18-bit bidirectional bus interface
- 3-state buffers
- Output capability: +64 mA and -32 mA
- TTL input and output switching levels
- Input and output interface capability to systems at 5 V supply
- Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
- Live insertion/extraction permitted
- Power-up reset
- Power-up 3-state
- No bus current loading when output is tied to 5 V bus
- Negative edge-triggered clock inputs
- Latch-up protection:
- JESD78: exceeds 500 mA
- ESD protection:
- MIL STD 883 Method 3015: exceeds 2000 V
- CDM JESD22-C101-C exceeds 1000 V
Documentation (4)
File name | Title | Type | Date |
---|---|---|---|
74LVT16500A | 3.3 V 18-bit universal bus transceiver; 3-state | Data sheet | 2006-05-28 |
lvt16500a | lvt16500a IBIS model | IBIS model | 2013-04-07 |
Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
lvt16 | lvt16 Spice model | SPICE model | 2013-05-06 |
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