74AVC1T1004

1-to-4 fan-out buffer

The 74AVC1T1004 is a translating 1-to-4 fan-out buffer suitable for use in clock distribution. It has dual supplies (VCC(A) and VCC(B)) for voltage translation. It also has a data input (A), four data outputs (Yn) and an output enable input (OE). VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V. It makes the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The levels of A and OE are referenced to VCC(A), outputs Yn are referenced to VCC(B). This supply configuration ensures that the fanned out signals can be used in level shifting. A HIGH on OE causes all outputs to be pulled LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors and enables all outputs.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range:
    • VCC(A): 0.8 V to 3.6 V
    • VCC(B): 0.8 V to 3.6 V
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
    • CDM JESD22-C101 exceeds 1000 V
  • Maximum data rates:
    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
    • 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
    • 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
    • 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
    • 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AVC1T1004DPProduction0.8 - 3.60.8 - 3.6CMOS/LVTTL± 124.91very low-40~12518823.85440484848596.7835975757576TSSOP10
74AVC1T1004GU33Production0.8 - 3.60.8 - 3.6CMOS/LVTTL± 124.91very low-40~125X2QFN10

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AVC1T1004DP
TSSOP10
(SOT552-1)
SOT552-1SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1ActiveStandard Marking74AVC1T1004DPJ
( 9356 901 22118 )
74AVC1T1004GU33
X2QFN10
(SOT1430-1)
SOT1430-1Reel 7" Q1/T1 in Sulfur Barrier BagActiveStandard Marking74AVC1T1004GU33Z
( 9356 901 26471 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AVC1T1004DP74AVC1T1004DPJ74AVC1T1004DPweek 25, 201911
74AVC1T1004GU3374AVC1T1004GU33Z74AVC1T1004GU33week 25, 201911
Quality and reliability disclaimer

Documentation (7)

File nameTitleTypeDate
74AVC1T10041-to-4 fan-out bufferData sheet2018-04-23
avc1t100474AVC1T1004 IBIS modelIBIS model2018-06-18
SOT552-1_118TSSOP10; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-16
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT552-1plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm bodyOutline drawing2018-11-14
SOT1430-1_471X2QFN10; Reel sulfur barrier pack, SMD, 7" Q1/T1 standard product orientation Orderable part number ending ,471 or Z Ordering code (12NC) ending 471Packing2017-11-17
SOT1430-1plastic, leadless extremely thin small outline package; 10 terminals; body 1.6 x 1.3 x 0.33 mmOutline drawing2019-01-07

Support

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Models

File nameTitleTypeDate
avc1t100474AVC1T1004 IBIS modelIBIS model2018-06-18

Ordering, pricing & availability

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