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74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G74DCProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12520636.4117VSSOP8
74LVC1G74DPProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12522021.3107TSSOP8
74LVC1G74GF
NRND
Not for design in----------XSON8
74LVC1G74GNProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12524712.1155XSON8
74LVC1G74GSProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12528412.3152XSON8
74LVC1G74GTProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~1253396.8166XSON8

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC1G74DC
VSSOP8
(SOT765-1)
SOT765-1Reel 7" Q3/T4, ReverseActiveV7474LVC1G74DC,125
( 9352 749 73125 )
74LVC1G74DP
TSSOP8
(SOT505-2)
SOT505-2Reel 7" Q3/T4, ReverseActiveV7474LVC1G74DP,125
( 9352 749 74125 )
74LVC1G74GF
NRND

XSON8
(SOT1089)
SOT1089Reel 7” Q1/T1 or Q2/T3ActiveY474LVC1G74GF,115
( 9352 905 07115 )
74LVC1G74GN
XSON8
(SOT1116)
SOT1116Reel 7” Q1/T1 or Q2/T3ActiveY474LVC1G74GN,115
( 9352 922 35115 )
74LVC1G74GS
XSON8
(SOT1203)
SOT1203Reel 7” Q1/T1 or Q2/T3ActiveY474LVC1G74GS,115
( 9352 927 95115 )
74LVC1G74GT
XSON8
(SOT833-1)
SOT833-1Reel 7” Q1/T1 or Q2/T3ActiveV7474LVC1G74GT,115
( 9352 789 17115 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74LVC1G74DC74LVC1G74DC,12574LVC1G74DCweek 1, 200519.30.52E911
74LVC1G74DP74LVC1G74DP,125Not available
You can request this via a support request
week 41, 200419.30.52E911
74LVC1G74GF
NRND
74LVC1G74GF,11574LVC1G74GFAlways Pb-free11
74LVC1G74GN74LVC1G74GN,11574LVC1G74GNAlways Pb-free19.30.52E911
74LVC1G74GS74LVC1G74GS,11574LVC1G74GSAlways Pb-free19.30.52E911
74LVC1G74GT74LVC1G74GT,115Not available
You can request this via a support request
Always Pb-free19.30.52E911
Quality and reliability disclaimer

Documentation (16)

File nameTitleTypeDate
74LVC1G74Single D-type flip-flop with set and reset; positive edge triggerData sheet2021-09-20
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc1g7474LVC1G74 IBIS modelIBIS model2014-10-20
Nexperia_Selection_guide_2020Nexperia Selection Guide 2020Selection guide2020-01-31
Nexperia_Selection_guide_2021Nexperia Selection Guide 2021Selection guide2021-01-08
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyPackage information2020-04-21
SOT1089plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.5 mm bodyPackage information2020-04-21
MAR_SOT1089MAR_SOT1089 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyPackage information2020-04-21
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2020-04-21
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2020-04-21
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyPackage information2020-04-21
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03

Support

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Models

File nameTitleTypeDate
lvc1g7474LVC1G74 IBIS modelIBIS model2014-10-20

Sample

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