74AUP2G125

Low-power dual buffer/line driver; 3-state

The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE) is HIGH.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78B Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • Input-disable feature allows floating input conditions
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from –40 ℃ to +85 ℃ and –40 ℃ to +125 ℃

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationsRth(j-a) (K/W)Rth(j-c) (K/W)Package name
74AUP2G125DCProduction0.8 - 3.6CMOS± 1.9702ultra low203113VSSOP8
74AUP2G125GF
NRND
Not for design inXSON8
74AUP2G125GNProduction0.8 - 3.6CMOS± 1.9702ultra low238148XSON8
74AUP2G125GSProduction0.8 - 3.6CMOS± 1.9702ultra low276146XSON8
74AUP2G125GTProduction0.8 - 3.6CMOS± 1.9702ultra low327157XSON8
74AUP2G125GXProduction0.8 - 3.6CMOS± 1.9702ultra lowX2SON8

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP2G125DC
VSSOP8
(SOT765-1)
SOT765-1Reel 7" Q3/T4, ReverseActivep2574AUP2G125DC,125
( 9352 807 27125 )
74AUP2G125GF
NRND

XSON8
(SOT1089)
SOT1089Reel 7” Q1/T1 or Q2/T3ActiveaM74AUP2G125GF,115
( 9352 905 49115 )
74AUP2G125GN
XSON8
(SOT1116)
SOT1116Reel 7” Q1/T1 or Q2/T3ActiveaM74AUP2G125GN,115
( 9352 889 88115 )
74AUP2G125GS
XSON8
(SOT1203)
SOT1203Reel 7” Q1/T1 or Q2/T3ActiveaM74AUP2G125GS,115
( 9352 927 82115 )
74AUP2G125GT
XSON8
(SOT833-1)
SOT833-1Reel 7” Q1/T1 or Q2/T3Activep2574AUP2G125GT,115
( 9352 807 28115 )
74AUP2G125GX
X2SON8
(SOT1233)
SOT1233Reel 7” Q1/T1 or Q2/T3ActiveStandard Marking74AUP2G125GXX
( 9353 084 42115 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AUP2G125DC74AUP2G125DC,12574AUP2G125DCAlways Pb-free11
74AUP2G125GF
NRND
74AUP2G125GF,11574AUP2G125GFAlways Pb-free11
74AUP2G125GN74AUP2G125GN,11574AUP2G125GNAlways Pb-free11
74AUP2G125GS74AUP2G125GS,11574AUP2G125GSAlways Pb-free11
74AUP2G125GT74AUP2G125GT,11574AUP2G125GTAlways Pb-free11
74AUP2G125GX74AUP2G125GXX74AUP2G125GXweek 25, 201911
Quality and reliability disclaimer

Documentation (17)

File nameTitleTypeDate
74AUP2G125Low-power dual buffer/line driver; 3-stateData sheet2017-07-14
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup2g125aup2g125 IBIS modelIBIS model2013-04-07
Nexperia_document_leaflet_Logic_X2SON_packages_062018X2SON ultra-small 4, 5, 6 & 8-pin leadless packagesLeaflet2018-06-05
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_Selection_guide_2020Nexperia Selection Guide 2020Selection guide2020-01-31
MAR_SOT1089MAR_SOT1089 TopmarkTop marking2013-06-03
SOT1089plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.5 mm bodyPackage information2020-04-21
SOT1233plastic, leadless thermal enhanced extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1.35 mm x 0.8 mm x 0.35 mm bodyPackage information2020-04-21
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyPackage information2020-04-21
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2020-04-21
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2020-04-21
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyPackage information2020-04-21

Support

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Models

File nameTitleTypeDate
aup2g125aup2g125 IBIS modelIBIS model2013-04-07

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