16-bit bus transceiver/register; 3-state

The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (nCPAB or nCPBA) goes to a HIGH logic level. Output enable (nOE) and direction (nDIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both. The select source inputs (nSAB and nSBA) can multiplex stored and real-time (transparent mode) data. The direction (nDIR) input determines which bus will receive data when nOE is active (LOW). In the isolation mode (nOE = HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may be stored in the ‘A’ register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, ‘A’ or ‘B’ may be driven at a time.

To ensure the high impedance state during power up or power down, nOE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Features and benefits

  • Wide supply voltage range of 2.3 V to 3.6 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • Current drive ±24 mA at VCC = 3.0 V.
  • MULTIBYTE flow-through standard pin-out architecture
  • Low inductance multiple VCC and GND pins for minimize noise and ground bounce
  • All data inputs have bushold
  • Output drive capability 50 Ω transmission lines at 85 °C
  • Complies with JEDEC standards:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    • CDM JESD22-C101E exceeds 1000 V


Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capabilitytpd (ns)No of bitsfmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVCH16646DGGProduction1.65 - 3.6n.a.TTL+/- 242.616150low-40~859321.0TSSOP56


Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
Tube in DrypackActiveALVCH1664674ALVCH16646DGGS
( 9352 624 21512 )
Reel 13" Q1/T1 in DrypackActiveALVCH1664674ALVCH16646DGGY
( 9352 624 21518 )

Discontinuation information

Type numberOrderable part number, (Ordering code (12NC))Last time buy dateLast time delivery dateReplacement productStatusComments

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74ALVCH16646DGG74ALVCH16646DGGS74ALVCH16646DGGAlways Pb-free123.83.872.58E822
74ALVCH16646DGG74ALVCH16646DGGY74ALVCH16646DGGAlways Pb-free123.83.872.58E822
Quality and reliability disclaimer

Documentation (4)

File nameTitleTypeDate
74ALVCH1664616-bit bus transceiver/register; 3-stateData sheet2018-09-11
alvch16646alvch16646 IBIS modelIBIS model2013-04-07
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyPackage information2020-04-21


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File nameTitleTypeDate
alvch16646alvch16646 IBIS modelIBIS model2013-04-07

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