74AVC4T774

4-bit dual supply translating transceiver; 3-state

The 74AVC4T774 is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input (OE) and dual supply pins (V_CC(A) and V_CC(B)). Both V_CC(A) and V_CC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced to V_CC(A) and pins Bn are referenced to V_CC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

Features

Wide supply voltage range:
- V_CC(A): 0.8 V to 3.6 V
- V_CC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114E Class 3B exceeds 8000 V
- CDM JESD22-C101C exceeds 1500 V
Maximum data rates:
- 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
- 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
- 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
- 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
- 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
- 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I_OFF circuitry provides partial Power-down mode operation
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number	Product status	V_CC(A) (V)	V_CC(B) (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AVC4T774BQ	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	+/- 12	2.1	4	very low	-40~125	92	13.0	61	DHVQFN16
74AVC4T774GU	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	+/- 12	2.1	4	very low	-40~125	99	4.1	87	XQFN16

Package

Type number	Package	Outline version	Reflow-/Wave soldering	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AVC4T774BQ	DHVQFN16 (SOT763-1)	SOT763-1		Reel 7" Q1/T1	Active	Standard Marking	74AVC4T774BQX ( 9353 413 26115 )
74AVC4T774GU	XQFN16 (SOT1161-1)	SOT1161-1		Reel 7" Q1/T1	Active	Standard Marking	74AVC4T774GUX ( 9353 413 27115 )

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	RoHS / RHF	Leadfree conversion date	MSL	MSL leadfree
74AVC4T774BQ	74AVC4T774BQX	74AVC4T774BQ		week 25, 2019	1	1
74AVC4T774GU	74AVC4T774GUX	74AVC4T774GU		week 25, 2019	1	1

Quality and reliability disclaimer

Documentation (7)

File name	Title	Type	Date
74AVC4T774	4-bit dual supply translating transceiver; 3-state	Data sheet	2017-10-02
Nexperia_document_guide_Logic_translators_201711	Nexperia Logic Translators	Brochure	2017-12-05
avc4t774	AVC4T774 IBIS model	IBIS model	2017-10-04
SOT763-1_115	DHVQFN16; Reel pack, SMD, 7" Q1/T1 standard product orientation Orderable part number ending ,115 or X Ordering code (12NC) ending 115	Packing	2016-07-05
SOT763-1	plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 16 terminals; 0.5 mm pitch; 3.5 mm x 2.5 mm x 1 mm body	Outline drawing	2018-11-14
SOT1161-1_115	Standard product orientation 12NC ending 115	Packing	2013-04-05
SOT1161-1	plastic, leadless extermely thin quad flat package; 16 terminals; 0.4 mm pitch; 2.6 mm x 1.8 mm x 0.5 mm body	Outline drawing	2018-11-14

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Models

File name	Title	Type	Date
avc4t774	AVC4T774 IBIS model	IBIS model	2017-10-04

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