74AUP1G885

Low-power dual function gate

The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A × C. The output 2Y provides the Boolean function: 2Y = A × B + A × C.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G885DCProduction1.1 - 3.6CMOS+/- 1.97.6701ultra low-40~12520334.1113VSSOP8
74AUP1G885GF
NRND
Not for design in1.1 - 3.6CMOS+/- 1.97.6701ultra low-40~1252542.1124XSON8
74AUP1G885GNProduction1.1 - 3.6CMOS+/- 1.97.6701ultra low-40~12523810.6148XSON8
74AUP1G885GSProduction1.1 - 3.6CMOS+/- 1.97.6701ultra low-40~12527610.8146XSON8
74AUP1G885GTProduction1.1 - 3.6CMOS+/- 1.97.6701ultra low-40~1253276.1157XSON8

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP1G885DC
VSSOP8
(SOT765-1)
SOT765-1Reel 7" Q3/T4, ReverseActivepS874AUP1G885DC,125
( 9352 807 65125 )
74AUP1G885GF
NRND

XSON8
(SOT1089)
SOT1089Reel 7" Q1/T1Active5874AUP1G885GF,115
( 9352 914 72115 )
74AUP1G885GN
XSON8
(SOT1116)
SOT1116Reel 7" Q1/T1Active5874AUP1G885GN,115
( 9352 922 16115 )
74AUP1G885GS
XSON8
(SOT1203)
SOT1203Reel 7" Q1/T1Active5874AUP1G885GS,115
( 9352 927 77115 )
74AUP1G885GT
XSON8
(SOT833-1)
SOT833-1Reel 7" Q1/T1ActivepS874AUP1G885GT,115
( 9352 807 67115 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74AUP1G885DC74AUP1G885DC,12574AUP1G885DCAlways Pb-free0.03.293.04E811
74AUP1G885GF
NRND
74AUP1G885GF,11574AUP1G885GFAlways Pb-free11
74AUP1G885GN74AUP1G885GN,11574AUP1G885GNAlways Pb-free11
74AUP1G885GS74AUP1G885GS,11574AUP1G885GSAlways Pb-free11
74AUP1G885GT74AUP1G885GT,11574AUP1G885GTAlways Pb-free0.03.293.04E811
Quality and reliability disclaimer

Documentation (20)

File nameTitleTypeDate
74AUP1G885Low-power dual function gateData sheet2019-03-14
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup1g885aup1g885 IBIS modelIBIS model2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
nexperia_selection_guide_2019_201901Selection guide 2019. Discretes, Logic and MOSFETsSelection guide2018-12-12
SOT1089_115XSON8; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering code (12NC) ending 115Packing2013-04-23
MAR_SOT1089MAR_SOT1089 TopmarkTop marking2013-06-03
SOT1089plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.5 mm bodyOutline drawing2019-05-28
SOT1203_115Standard product orientation 12NC ending 115Packing2013-07-03
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyOutline drawing2018-11-14
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1_115Standard product orientation 12NC ending 115Packing2013-04-05
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyOutline drawing2018-11-14
SOT765-1_125VSSOP8; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or H Ordering code (12NC) ending 125Packing2013-05-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyOutline drawing2018-11-14
SOT1116_115Standard product orientation 12NC ending 115Packing2013-04-04
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyOutline drawing2018-11-14

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Models

File nameTitleTypeDate
aup1g885aup1g885 IBIS modelIBIS model2013-04-07

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