74AUP1G885

Low-power dual function gate

The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A × C. The output 2Y provides the Boolean function: 2Y = A × B + A × C.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1G885DC	Production	0.8 - 3.6	CMOS	± 1.9	7.6	70	1	ultra low	-40~125	203	34.1	113	VSSOP8
74AUP1G885GF NRND	Not for design in	-	-	-	-	-	-	-	-	-	-	-	XSON8
74AUP1G885GN	Production	0.8 - 3.6	CMOS	± 1.9	7.6	70	1	ultra low	-40~125	238	10.6	148	XSON8
74AUP1G885GS	Production	0.8 - 3.6	CMOS	± 1.9	7.6	70	1	ultra low	-40~125	276	10.8	146	XSON8
74AUP1G885GT	Production	0.8 - 3.6	CMOS	± 1.9	7.6	70	1	ultra low	-40~125	327	6.1	157	XSON8

Package

Type number	Package	Package information	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AUP1G885DC	VSSOP8 (SOT765-1)	SOT765-1	Reel 7" Q3/T4, Reverse	Active	pS8	74AUP1G885DC,125 ( 9352 807 65125 )
74AUP1G885GF NRND	XSON8 (SOT1089)	SOT1089	Reel 7” Q1/T1 or Q2/T3	Active	58	74AUP1G885GF,115 ( 9352 914 72115 )
74AUP1G885GN	XSON8 (SOT1116)	SOT1116	Reel 7” Q1/T1 or Q2/T3	Active	58	74AUP1G885GN,115 ( 9352 922 16115 )
74AUP1G885GS	XSON8 (SOT1203)	SOT1203	Reel 7” Q1/T1 or Q2/T3	Active	58	74AUP1G885GS,115 ( 9352 927 77115 )
74AUP1G885GT	XSON8 (SOT833-1)	SOT833-1	Reel 7” Q1/T1 or Q2/T3	Active	pS8	74AUP1G885GT,115 ( 9352 807 67115 )

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	Leadfree conversion date	EFR	IFR	MTBF (hour)	MSL	MSL leadfree
74AUP1G885DC	74AUP1G885DC,125	74AUP1G885DC	Always Pb-free	32.6	0.9	1.11E9	1	1
74AUP1G885GF NRND	74AUP1G885GF,115	74AUP1G885GF	Always Pb-free				1	1
74AUP1G885GN	74AUP1G885GN,115	74AUP1G885GN	Always Pb-free	32.6	0.9	1.11E9	1	1
74AUP1G885GS	74AUP1G885GS,115	74AUP1G885GS	Always Pb-free	32.6	0.9	1.11E9	1	1
74AUP1G885GT	74AUP1G885GT,115	74AUP1G885GT	Always Pb-free	32.6	0.9	1.11E9	1	1

Quality and reliability disclaimer

Documentation (16)

File name	Title	Type	Date
74AUP1G885	Low-power dual function gate	Data sheet	2019-07-22
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup1g885	aup1g885 IBIS model	IBIS model	2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_document_Logic_CombinationLogic_infocard_201710	Combination logic solutions card	Leaflet	2017-10-16
Nexperia_Selection_guide_2022	Nexperia Selection Guide 2022	Selection guide	2022-01-05
SOT1089	plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.5 mm body	Package information	2020-04-21
MAR_SOT1089	MAR_SOT1089 Topmark	Top marking	2013-06-03
SOT1203	plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body	Package information	2020-04-21
MAR_SOT1203	MAR_SOT1203 Topmark	Top marking	2013-06-03
SOT833-1	plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body	Package information	2020-04-21
MAR_SOT833	MAR_SOT833 Topmark	Top marking	2013-06-03
SOT765-1	plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body	Package information	2020-04-21
SOT1116	plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm body	Package information	2020-04-21
MAR_SOT1116	MAR_SOT1116 Topmark	Top marking	2013-06-03

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Models

File name	Title	Type	Date
aup1g885	aup1g885 IBIS model	IBIS model	2013-04-07

Ordering, pricing & availability

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