74AUP1G373-Q100

Low-power D-type transparent latch; 3-state

The 74AUP1G373-Q100 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latch. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
    • HBM JESD22-A114F Class 3A. Exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G373GW-Q100Production1.1 - 3.6CMOS1.9/-1.98.51ultra low-40~12526469.0153TSSOP6

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP1G373GW-Q100
TSSOP6
(SOT363)
SOT363Reel 7" Q3/T4, ReverseActiveaW74AUP1G373GW-Q100H
( 9353 030 15125 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AUP1G373GW-Q10074AUP1G373GW-Q100H74AUP1G373GW-Q100Always Pb-free11
Quality and reliability disclaimer

Documentation (11)

File nameTitleTypeDate
74AUP1G373_Q100Low-power D-type transparent latch; 3-stateData sheet2020-03-27
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup1g373aup1g373 IBIS modelIBIS model2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
SOT363_165TSSOP6; reel pack; reversed product orientation; 12NC ending 165Packing2012-11-20
SOT363_135TSSOP6; Tape reel SMD; standard product orientation 12NC ending 135Packing2012-11-20
MAR_SOT363MAR_SOT363 TopmarkTop marking2013-06-03
SOT363_115TSSOP6; Tape reel SMD; standard product orientation 12NC ending 115Packing2012-11-15
SOT363plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm bodyOutline drawing2018-11-14
SOT363_125TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientationPacking2020-02-14

Support

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Models

File nameTitleTypeDate
aup1g373aup1g373 IBIS modelIBIS model2014-12-21

Ordering, pricing & availability

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