74AUP1G09GF

Low-power 2-input AND gate with open-drain

The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G09GFProduction1.1 - 3.6CMOS1.98.5701ultra low-40~1253117.7157XSON6

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP1G09GF
XSON6
(SOT891)
SOT891Reflow_Soldering_Profile
Reel 7" Q1/T1, Q3/T4Activep974AUP1G09GF,132
( 9352 883 04132 )

Quality

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74AUP1G09GF74AUP1G09GF,13274AUP1G09GFAlways Pb-free0.03.293.04E811
Quality and reliability disclaimer

Documentation (11)

File nameTitleTypeDate
74AUP1G09Low-power 2-input AND gate with open-drainData sheet2017-05-03
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2011-05-06
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
75017511Voltage translation: How to manage mixed-voltage designs with NXP level translatorsBrochure2014-05-19
75017458NXP ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logicBrochure2014-10-12
aup1g0974AUP1G09 IBIS model IBIS model2014-12-14
75017285Logic selection guide 2016Selection guide2015-01-07
Reflow_Soldering_ProfileReflow Soldering ProfileReflow soldering2013-12-23
SOT891_132XSON6; reel pack; standard product orientation; 12NC ending 132Packing2014-08-26
SOT891plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 1 mm x 1 mm x 0.5 mm bodyOutline drawing2017-01-30

Support

Find answers to your design questions on this page. If available you can find information in our Nexperia Support Community or you can find Nexperia models and Design tools.

Models

File nameTitleTypeDate
aup1g0974AUP1G09 IBIS model IBIS model2014-12-14

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