74AUP1G74

Low-power D-type flip-flop with set and reset; positive-edge trigger

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1G74DC	Production	0.8 - 3.6	CMOS	± 1.9	9.2	400	ultra low	-40~125	203	34.1	113	VSSOP8
74AUP1G74GN	Production	0.8 - 3.6	CMOS	± 1.9	9.2	400	ultra low	-40~125	238	10.6	148	XSON8
74AUP1G74GS	Production	0.8 - 3.6	CMOS	± 1.9	9.2	400	ultra low	-40~125	276	10.8	146	XSON8
74AUP1G74GT	Production	0.8 - 3.6	CMOS	± 1.9	9.2	400	ultra low	-40~125	327	6.1	157	XSON8
74AUP1G74GX	Production	0.8 - 3.6	CMOS	± 1.9	9.2	400	ultra low	-40~125	256	6.5	148	X2SON8

Package

Type number	Package	Package information	Reflow-/Wave soldering	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AUP1G74DC	VSSOP8 (SOT765-1)	SOT765-1		SOT765-1_125	Active	p74	74AUP1G74DC,125 ( 9352 807 17125 )
74AUP1G74GN	XSON8 (SOT1116)	SOT1116	REFLOW_BG-BD-1	SOT1116_115	Active	54	74AUP1G74GN,115 ( 9352 922 15115 )
74AUP1G74GS	XSON8 (SOT1203)	SOT1203	REFLOW_BG-BD-1	SOT1203_115	Active	54	74AUP1G74GS,115 ( 9352 927 75115 )
74AUP1G74GT	XSON8 (SOT833-1)	SOT833-1		SOT833-1_115	Active	p74	74AUP1G74GT,115 ( 9352 807 18115 )
74AUP1G74GX	X2SON8 (SOT1233-2)	SOT1233-2		SOT1233-2_115	Active	54	74AUP1G74GXX ( 9353 084 41115 )

Environmental information

Type number	Orderable part number	Chemical content	Leadfree conversion date
74AUP1G74DC	74AUP1G74DC,125	74AUP1G74DC	Always Pb-free
74AUP1G74GN	74AUP1G74GN,115	74AUP1G74GN	Always Pb-free
74AUP1G74GS	74AUP1G74GS,115	74AUP1G74GS	Always Pb-free
74AUP1G74GT	74AUP1G74GT,115	74AUP1G74GT	Always Pb-free
74AUP1G74GX	74AUP1G74GXX	74AUP1G74GX	week 25, 2019

Quality and reliability disclaimer

Documentation (17)

File name	Title	Type	Date
74AUP1G74	Low-power D-type flip-flop with set and reset; positive-edge trigger	Data sheet	2023-07-14
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup1g74	aup1g74 IBIS model	IBIS model	2013-04-07
Nexperia_document_leaflet_Logic_X2SON_packages_062018	X2SON ultra-small 4, 5, 6 & 8-pin leadless packages	Leaflet	2018-06-05
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10
SOT1233-2	plastic thermal enhanced extremely thin small outline package; no leads;8 terminals; body 1.35 x 0.8 x 0.32 mm	Package information	2022-04-21
MAR_SOT1203	MAR_SOT1203 Topmark	Top marking	2013-06-03
SOT1203	plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body	Package information	2022-06-03
REFLOW_BG-BD-1	Reflow soldering profile	Reflow soldering	2021-04-06
MAR_SOT833	MAR_SOT833 Topmark	Top marking	2013-06-03
SOT833-1	plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body	Package information	2022-06-03
SOT765-1	plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body	Package information	2022-06-03
MAR_SOT1116	MAR_SOT1116 Topmark	Top marking	2013-06-03
SOT1116	plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm body	Package information	2022-06-02
REFLOW_BG-BD-1	Reflow soldering profile	Reflow soldering	2021-04-06

Support

If you are in need of design/technical support, let us know and fill in the answer form, we'll get back to you shortly.

Models

File name	Title	Type	Date
aup1g74	aup1g74 IBIS model	IBIS model	2013-04-07

Ordering, pricing & availability

Sample

As a Nexperia customer you can order samples via our sales organization or directly via our Online Sample Store: https://extranet.nexperia.com.

Sample orders normally take 2-4 days for delivery.

If you do not have a direct account with Nexperia our network of global and regional distributors is available and equipped to support you with Nexperia samples.