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74HC161D-Q100

Presettable synchronous 4-bit binary counter; asynchronous reset

The 74HC161-Q100 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

image

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74HC161D-Q100 74HC161D-Q100J 935304496118 SOT109-1 Order product

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • CMOS input levels
  • Synchronous counting and loading
  • 2 count enable inputs for n-bit cascading
  • Asynchronous reset
  • Positive-edge triggered clock
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

Applications

Parametrics

Type numberProduct statusVCC (V)Output drive capability (mA)Logic switching levelstpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74HC161D-Q100Production2.0 - 6.0± 5.2CMOS1944low-40~125835.241SO16

Package

Type numberOrderable part number, (Ordering code (12NC))StatusMarkingPackagePackage informationReflow-/Wave solderingPacking
74HC161D-Q10074HC161D-Q100J
( 9353 044 96118 )
Active74HC161D
SO16
(SOT109-1)
SOT109-1SO-SOJ-REFLOW
SO-SOJ-WAVE
Reel 13" Q1/T1

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFMSLMSL leadfree
74HC161D-Q10074HC161D-Q100J74HC161D-Q10011
Quality and reliability disclaimer

Documentation (5)

File nameTitleTypeDate
74HC161_Q100Presettable synchronous 4-bit binary counter; asynchronous resetData sheet2021-03-16
AN11044Pin FMEA 74HC/74HCT familyApplication note2019-01-09
HCT_USER_GUIDEHC/T User GuideUser manual1997-10-31
SO-SOJ-REFLOWFootprint for reflow solderingReflow soldering2009-10-08
SO-SOJ-WAVEFootprint for wave solderingWave soldering2009-10-08

Support

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Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74HC161D-Q10074HC161D-Q100J935304496118Reel 13" Q1/T1Order product

Sample

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