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74AUP1T97-Q100

Low-power configurable gate with voltage-level translator

The 74AUP1T97-Q100 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.

The 74AUP1T97-Q100 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 2.3 V to 3.6 V
  • High noise immunity
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 1.5 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1T97GW-Q100Production2.3 - 3.6CMOS± 1.98.7701ultra low-40~12526438.6153TSSOP6

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP1T97GW-Q100
TSSOP6
(SOT363)
SOT363WAVE_BG-BD-1
Reel 7" Q3/T4, ReverseActive5974AUP1T97GW-Q100H
( 9356 911 79125 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74AUP1T97GW-Q10074AUP1T97GW-Q100H74AUP1T97GW-Q10032.60.91.11E911
Quality and reliability disclaimer

Documentation (9)

File nameTitleTypeDate
74AUP1T97_Q100Low-power configurable gate with voltage-level translatorData sheet2021-07-15
Nexperia_document_guide_Logic_translatorsNexperia Logic TranslatorsBrochure2021-04-12
Nexperia_document_leaflet_Logic_X2SON_packages_062018X2SON ultra-small 4, 5, 6 & 8-pin leadless packagesLeaflet2018-06-05
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
wlcsp6_74aup1t97uk_3dwafer level chip-scale package; 6 bumps; 0.65 x 0.44 x 0.27 mmOutline 3d2017-01-30
Nexperia_Selection_guide_2021Nexperia Selection Guide 2021Selection guide2021-01-08
SOT363plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm bodyPackage information2020-04-21
MAR_SOT363MAR_SOT363 TopmarkTop marking2013-06-03
WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08

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