74AUP1G09

Low-power 2-input AND gate with open-drain

The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features and benefits

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1G09GF NRND	Not for design in	1.1 - 3.6	CMOS	1.9	8.5	70	1	ultra low	-40~125	311	7.7	157	XSON6
74AUP1G09GM	Production	0.8 - 3.6	CMOS	1.9	8.5	70	1	ultra low	-40~125	311	7.7	157	XSON6
74AUP1G09GN	Production	0.8 - 3.6	CMOS	1.9	8.5	70	1	ultra low	-40~125	334	22.6	207	XSON6
74AUP1G09GS	Production	0.8 - 3.6	CMOS	1.9	8.5	70	1	ultra low	-40~125	321	28.7	215	XSON6
74AUP1G09GW	Production	0.8 - 3.6	CMOS	1.9	8.5	70	1	ultra low	-40~125	309	79.2	179	TSSOP5
74AUP1G09GX	Production	0.8 - 3.6	CMOS	1.9	8.5	70	1	ultra low	-40~125	322	90.7	191	X2SON5

Package

Type number	Package	Package information	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AUP1G09GF NRND	XSON6 (SOT891)	SOT891	Reel 7" Q1/T1, Q3/T4	Active	p9	74AUP1G09GF,132 ( 9352 883 04132 )
74AUP1G09GM	XSON6 (SOT886)	SOT886	Reel 7" Q1/T1, Q3/T4	Active	p9	74AUP1G09GM,132 ( 9352 883 03132 )
74AUP1G09GM	XSON6 (SOT886)	SOT886	Reel 7” Q1/T1 or Q2/T3	Active	p9	74AUP1G09GM,115 ( 9352 883 03115 )
74AUP1G09GN	XSON6 (SOT1115)	SOT1115	Reel 7" Q1/T1, Q3/T4	Active	p9	74AUP1G09GN,132 ( 9352 917 19132 )
74AUP1G09GS	XSON6 (SOT1202)	SOT1202	Reel 7" Q1/T1, Q3/T4	Active	p9	74AUP1G09GS,132 ( 9352 928 35132 )
74AUP1G09GW	TSSOP5 (SOT353-1)	SOT353-1	Reel 7" Q3/T4, Reverse	Active	p9	74AUP1G09GW,125 ( 9352 883 02125 )
74AUP1G09GX	X2SON5 (SOT1226)	SOT1226	Reel 7" Q3/T4, Reverse	Active	p9	74AUP1G09GX,125 ( 9352 983 59125 )

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	Leadfree conversion date	EFR	IFR	MTBF (hour)	MSL	MSL leadfree
74AUP1G09GF NRND	74AUP1G09GF,132	74AUP1G09GF	Always Pb-free				1	1
74AUP1G09GM	74AUP1G09GM,132	74AUP1G09GM	Always Pb-free	0.0	3.29	3.04E8	1	1
74AUP1G09GM	74AUP1G09GM,115	74AUP1G09GM	Always Pb-free	0.0	3.29	3.04E8	1	1
74AUP1G09GN	74AUP1G09GN,132	74AUP1G09GN	Always Pb-free				1	1
74AUP1G09GS	74AUP1G09GS,132	74AUP1G09GS	Always Pb-free				1	1
74AUP1G09GW	74AUP1G09GW,125	74AUP1G09GW	Always Pb-free	0.0	3.29	3.04E8	1	1
74AUP1G09GX	74AUP1G09GX,125	74AUP1G09GX	Always Pb-free				1	1

Quality and reliability disclaimer

Documentation (18)

File name	Title	Type	Date
74AUP1G09	Low-power 2-input AND gate with open-drain	Data sheet	2017-09-29
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup1g09	74AUP1G09 IBIS model	IBIS model	2014-12-14
Nexperia_document_leaflet_Logic_X2SON_packages_062018	X2SON ultra-small 4, 5, 6 & 8-pin leadless packages	Leaflet	2018-06-05
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_Selection_guide_2020	Nexperia Selection Guide 2020	Selection guide	2020-01-31
MAR_SOT1202	MAR_SOT1202 Topmark	Top marking	2013-06-03
SOT1202	plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1mm x 0.35 mm body	Package information	2020-04-21
SOT353-1	plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body	Package information	2020-04-21
MAR_SOT1115	MAR_SOT1115 Topmark	Top marking	2013-06-03
SOT1115	plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm body	Package information	2020-04-21
MAR_SOT1226	MAR_SOT1226 Topmark	Top marking	2013-06-03
SOT1226	plastic, leadless thermal enhanced extremely thin small outline package; no leads; 5 terminals; 0.48 mm pitch; 0.8 mm x 0.8 mm x 0.35 mm body	Package information	2020-04-21
SOT891	plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm body	Package information	2020-04-21
MAR_SOT891	MAR_SOT891 Topmark	Top marking	2013-06-03
MAR_SOT886	MAR_SOT886 Topmark	Top marking	2013-06-03
SOT886	plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body	Package information	2020-04-21

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Models

File name	Title	Type	Date
aup1g09	74AUP1G09 IBIS model	IBIS model	2014-12-14

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