Orderable parts
| Type number | Orderable part number | Ordering code (12NC) | Package | Buy from distributors |
|---|---|---|---|---|
| 74AUP1G885GT | 74AUP1G885GT,115 | 935280767115 | SOT833-1 | Order product |
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Click here for more information74AUP1G885GT
Low-power dual function gate
The 74AUP1G885 is a dual function gate. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A × C. The output 2Y provides the Boolean function: 2Y = A × B + A × C.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Low static power consumption; ICC = 0.9 µA (maximum)
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 100 mA per JESD78 Class II
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Parametrics
| Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G885GT | 0.8 - 3.6 | CMOS | ± 1.9 | 7.6 | 70 | 1 | ultra low | -40~125 | 327 | 6.1 | 157 | XSON8 |
PCB Symbol, Footprint and 3D Model
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Package
| Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
|---|---|---|---|---|---|---|---|
| 74AUP1G885GT | 74AUP1G885GT,115 (935280767115) |
Active | pS8 |
XSON8 (SOT833-1) |
SOT833-1 | SOT833-1_115 |
Environmental information
| Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
|---|---|---|---|---|
| 74AUP1G885GT | 74AUP1G885GT,115 | 74AUP1G885GT |
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Series
Documentation (14)
| File name | Title | Type | Date |
|---|---|---|---|
| 74AUP1G885 | Low-power dual function gate | Data sheet | 2024-08-12 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| aup1g885 | aup1g885 IBIS model | IBIS model | 2013-04-07 |
| Nexperia_document_Logic_CombinationLogic_infocard_201710 | Combination logic solutions card | Leaflet | 2019-08-09 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT833-1 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body | Package information | 2022-06-03 |
| SOT833-1_115 | XSON8; Reel pack for SMD, 7''; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74AUP1G885GT_Nexperia_Product_Reliability | 74AUP1G885GT Nexperia Product Reliability | Quality document | 2025-03-20 |
| MAR_SOT833 | MAR_SOT833 Topmark | Top marking | 2013-06-03 |
Support
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Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
| Model Name | Description |
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Ordering, pricing & availability
| Type number | Orderable part number | Ordering code (12NC) | Status | Packing | Packing Quantity | Buy online |
|---|---|---|---|---|---|---|
| 74AUP1G885GT | 74AUP1G885GT,115 | 935280767115 | Active | SOT833-1_115 | 5,000 |
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Sample
As a Nexperia customer you can order samples via our sales organization.
If you do not have a direct account with Nexperia our network of global and regional distributors is available and equipped to support you with Nexperia samples. Check out the list of official distributors.
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.