74AUP1G885GT

Low-power dual function gate

The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A × C. The output 2Y provides the Boolean function: 2Y = A × B + A × C.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Low-power dual function gate

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Seller	SKU	Stock	MOQ		1	10	100	1,000	10,000	Purchase

Seller	SKU	Stock	MOQ		1	10	100	1,000	10,000	Purchase

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* Stock values are subject to change
** Displayed price per unit is based on small quantity orders
*** Authorized resellers for overstock, mature, and discontinued products which are warranted for reliability by the reseller, no longer by Nexperia

Features and benefits

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1G885GT	Production	0.8 - 3.6	CMOS	± 1.9	7.6	70	1	ultra low	-40~125	327	6.1	157	XSON8

Package

Type number	Orderable part number, (Ordering code (12NC))	Status	Marking	Package	Package information	Reflow-/Wave soldering	Packing
74AUP1G885GT	74AUP1G885GT,115 ( 9352 807 67115 )	Active	pS8	XSON8 (SOT833-1)	SOT833-1		Reel 7” Q1/T1 or Q2/T3

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	RoHS / RHF	Leadfree conversion date	MSL	MSL leadfree
74AUP1G885GT	74AUP1G885GT,115	74AUP1G885GT		Always Pb-free	1	1

Quality and reliability disclaimer

Series

74AUP1G885 - Low-power dual function gate

Documentation (8)

File name	Title	Type	Date
74AUP1G885	Low-power dual function gate	Data sheet	2019-07-22
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN10343	MicroPak soldering information	Application note	2021-05-31
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup1g885	aup1g885 IBIS model	IBIS model	2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_document_Logic_CombinationLogic_infocard_201710	Combination logic solutions card	Leaflet	2017-10-16
74AUP1G885GT_Nexperia_Product_Reliability	74AUP1G885GT Nexperia Product Reliability	Quality document	2022-05-04

Support

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Models

File name	Title	Type	Date
aup1g885	aup1g885 IBIS model	IBIS model	2013-04-07

Ordering, pricing & availability

Type number	Orderable part number	Ordering code (12NC)	Packing	Packing quantity	Buy online
74AUP1G885GT	74AUP1G885GT,115	935280767115	Reel 7” Q1/T1 or Q2/T3	-	Order product

Sample

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