74AUP1G0832

Low-power 3-input AND-OR gate

The 74AUP1G0832 provides the Boolean function: Y = (A × B) + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to V_CC or GND.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1G0832GF NRND	Not for design in	1.1 - 3.6	CMOS	+/- 1.9	6.7	70	1	ultra low	-40~125	290	6.5	145	XSON6
74AUP1G0832GM	Production	1.1 - 3.6	CMOS	+/- 1.9	6.7	70	1	ultra low	-40~125	290	6.5	145	XSON6
74AUP1G0832GN	Production	1.1 - 3.6	CMOS	+/- 1.9	6.7	70	1	ultra low	-40~125	275	11.7	171	XSON6
74AUP1G0832GS	Production	1.1 - 3.6	CMOS	+/- 1.9	6.7	70	1	ultra low	-40~125	272	14.8	177	XSON6
74AUP1G0832GW	Production	1.1 - 3.6	CMOS	+/- 1.9	6.7	70	1	ultra low	-40~125	264	38.6	153	TSSOP6

Package

Type number	Package	Outline version	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AUP1G0832GF NRND	XSON6 (SOT891)	SOT891	Reel 7" Q1/T1, Q3/T4	Active	aY	74AUP1G0832GF,132 ( 9352 813 26132 )
74AUP1G0832GM	XSON6 (SOT886)	SOT886	Reel 7" Q1/T1, Q3/T4	Active	aY	74AUP1G0832GM,132 ( 9352 806 19132 )
74AUP1G0832GM	XSON6 (SOT886)	SOT886	Reel 7" Q1/T1	Active	aY	74AUP1G0832GM,115 ( 9352 806 19115 )
74AUP1G0832GN	XSON6 (SOT1115)	SOT1115	Reel 7" Q1/T1, Q3/T4	Active	aY	74AUP1G0832GN,132 ( 9352 917 17132 )
74AUP1G0832GS	XSON6 (SOT1202)	SOT1202	Reel 7" Q1/T1, Q3/T4	Active	aY	74AUP1G0832GS,132 ( 9352 928 32132 )
74AUP1G0832GW	TSSOP6 (SOT363)	SOT363	Reel 7" Q3/T4, Reverse	Active	aY	74AUP1G0832GW,125 ( 9352 806 18125 )

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	Leadfree conversion date	EFR	IFR	MTBF (hour)	MSL	MSL leadfree
74AUP1G0832GF NRND	74AUP1G0832GF,132	74AUP1G0832GF	Always Pb-free				1	1
74AUP1G0832GM	74AUP1G0832GM,132	74AUP1G0832GM	Always Pb-free	0.0	3.29	3.04E8	1	1
74AUP1G0832GM	74AUP1G0832GM,115	74AUP1G0832GM	Always Pb-free	0.0	3.29	3.04E8	1	1
74AUP1G0832GN	74AUP1G0832GN,132	74AUP1G0832GN	Always Pb-free				1	1
74AUP1G0832GS	74AUP1G0832GS,132	74AUP1G0832GS	Always Pb-free				1	1
74AUP1G0832GW	74AUP1G0832GW,125	74AUP1G0832GW	Always Pb-free	0.0	3.29	3.04E8	1	1

Quality and reliability disclaimer

Documentation (26)

File name	Title	Type	Date
74AUP1G0832	Low-power 3-input AND-OR gate	Data sheet	2017-05-03
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup1g0832	aup1g0832 IBIS model	IBIS model	2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_document_Logic_CombinationLogic_infocard_201710	Combination logic solutions card	Leaflet	2017-10-16
nexperia_selection_guide_2019_201901	Selection guide 2019. Discretes, Logic and MOSFETs	Selection guide	2018-12-12
MAR_SOT1202	MAR_SOT1202 Topmark	Top marking	2013-06-03
SOT1202_132	Reversed product orientation 12NC ending 132	Packing	2013-04-04
SOT1202	plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1mm x 0.35 mm body	Outline drawing	2018-11-14
MAR_SOT1115	MAR_SOT1115 Topmark	Top marking	2013-06-03
SOT1115_132	Reversed product orientation 12NC ending 132	Packing	2013-04-04
SOT1115	plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm body	Outline drawing	2018-11-14
MAR_SOT891	MAR_SOT891 Topmark	Top marking	2013-06-03
SOT891_132	XSON6; reel pack; standard product orientation; 12NC ending 132	Packing	2014-08-26
SOT891	plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm body	Outline drawing	2018-11-14
SOT363_165	TSSOP6; reel pack; reversed product orientation; 12NC ending 165	Packing	2012-11-20
SOT363_125	Tape reel SMD; reversed product orientation 12NC ending 125	Packing	2012-11-20
SOT363_135	TSSOP6; Tape reel SMD; standard product orientation 12NC ending 135	Packing	2012-11-20
MAR_SOT363	MAR_SOT363 Topmark	Top marking	2013-06-03
SOT363_115	TSSOP6; Tape reel SMD; standard product orientation 12NC ending 115	Packing	2012-11-15
SOT363	plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm body	Outline drawing	2018-11-14
SOT886_115	XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering code (12NC) ending 115	Packing	2013-04-23
MAR_SOT886	MAR_SOT886 Topmark	Top marking	2013-06-03
SOT886_132	XSON6; reel pack; standard product orientation; 12NC ending 132	Packing	2012-11-28
SOT886	plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body	Outline drawing	2018-11-14

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Models

File name	Title	Type	Date
aup1g0832	aup1g0832 IBIS model	IBIS model	2014-12-21

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