74AUP1T57GW

Low-power configurable gate with voltage-level translator

The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.

The 74AUP1T57 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74AUP1T57GW 74AUP1T57GW,125 935280464125 SOT363 Order product

Features

  • Wide supply voltage range from 2.3 V to 3.6 V
  • High noise immunity
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 1.5 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1T57GWProduction2.3 - 3.6CMOS± 1.98.7701ultra low-40~12526438.6153TSSOP6

Package

Type numberOrderable part number, (Ordering code (12NC))StatusMarkingPackageOutline versionReflow-/Wave solderingPacking
74AUP1T57GW74AUP1T57GW,125
( 9352 804 64125 )
Activea7
TSSOP6
(SOT363)
SOT363Reel 7" Q3/T4, Reverse

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFMSLMSL leadfree
74AUP1T57GW74AUP1T57GW,12574AUP1T57GW11
Quality and reliability disclaimer

Documentation (6)

File nameTitleTypeDate
74AUP1T57Low-power configurable gate with voltage-level translatorData sheet2017-05-03
AN10161PicoGate Logic footprintsApplication note2002-10-29
aup1t57aup1t57 IBIS modelIBIS model2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
SOT363_125Tape reel SMD; reversed product orientation 12NC ending 125Packing2012-11-20
SOT363plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm bodyOutline drawing2018-11-14

Support

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Models

File nameTitleTypeDate
aup1t57aup1t57 IBIS modelIBIS model2014-12-21

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74AUP1T57GW74AUP1T57GW,125935280464125Reel 7" Q3/T4, ReverseOrder product

Sample

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Sample orders normally take 2-4 days for delivery.

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