74AUP1T97GF

Low-power configurable gate with voltage-level translator

NRND

The 74AUP1T97 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to V_CC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire V_CC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Not recommended for new designs (NRND).

This product has been discontinued, click here for discontinuation information and replacement parts.

Alternatives

74AUP1T97GS

Recommended replacement

Low-power configurable gate with voltage-level translator

Buy from Nexperia

SKU	Stock*	MOQ	Price per unit**	Quantity

Buy from distributors

Seller	SKU	Stock	MOQ		1	10	100	1,000	10,000	Purchase

Seller	SKU	Stock	MOQ		1	10	100	1,000	10,000	Purchase

Seller	SKU	Stock	MOQ		1	10	100	1,000	10,000	Purchase

Seller	SKU	Stock	MOQ		1	10	100	1,000	10,000	Purchase

* Stock values are subject to change
** Displayed price per unit is based on small quantity orders
*** Authorized resellers for overstock, mature, and discontinued products which are warranted for reliability by the reseller, no longer by Nexperia

Features and benefits

Wide supply voltage range from 2.3 V to 3.6 V
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II
Low static power consumption; I_CC = 1.5 μA (maximum)
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

Parametrics

Type number	Product status	Package name
74AUP1T97GF NRND	Not for design in	XSON6

Package

All type numbers in the table below are discontinued. See the table Discontinuation information for more information.

Type number	Orderable part number, (Ordering code (12NC))	Status	Marking	Package	Package information	Reflow-/Wave soldering	Packing
74AUP1T97GF NRND	74AUP1T97GF,132 ( 9352 813 66132 )	Withdrawn / End-of-life	59	XSON6 (SOT891)	SOT891		Reel 7" Q1/T1, Q3/T4

Discontinuation information

Type number	Orderable part number	Ordering code	Last time buy date	Last time delivery date	Replacement product	Status	Comments
74AUP1T97GF NRND	74AUP1T97GF,132	935281366132	2021-06-30	2021-12-31	74AUP1T97GS	Version withdrawal

Quality, reliability & chemical content

All type numbers in the table below are discontinued. See the table Discontinuation information for more information.

Type number	Orderable part number	Chemical content	RoHS / RHF	Leadfree conversion date	MSL	MSL leadfree
74AUP1T97GF NRND	74AUP1T97GF,132	Not available		Always Pb-free	1	1

Quality and reliability disclaimer

Series

Documentation (5)

File name	Title	Type	Date
74AUP1T97	Low-power configurable gate with voltage-level translator	Data sheet	2022-01-27
AN10161	PicoGate Logic footprints	Application note	2002-10-29
Nexperia_document_guide_Logic_translators	Nexperia Logic Translators	Brochure	2021-04-12
aup1t97	aup1t97 IBIS model	IBIS model	2015-09-06
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12

Support

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Models

File name	Title	Type	Date
aup1t97	aup1t97 IBIS model	IBIS model	2015-09-06