74AHC257PW

The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74AHC257; 74AHCT257 is the logic implementation of a 4-pole 2-position switch, where the position of the switch is determined by the logic levels applied to input S. The outputs are forced to a high-impedance OFF-state when OE is HIGH.

The logic equations for the outputs are:

• 1Y = OE x (1I1 x S + 1I0 x S)
• 2Y = OE x (2I1 x S + 2I0 x S)
• 3Y = OE x (3I1 x S + 3I0 x S)
• 4Y = OE x (4I1 x S + 4I0 x S)

The 74AHC257; 74AHCT257 is identical to the 74AHC258; 74AHCT258, but has non-inverting (true) outputs.