HEF4518BT

The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of the nCP0 input if nCP1 is HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0, nCP1. Schmitt trigger action in the clock input makes the circuit highly tolerant of slower clock rise and fall times.

It operates over a recommended V_DD power supply range of 3 V to 15 V referenced to V_SS (usually ground). Unused inputs must be connected to V_DD, V_SS, or another input.