74LVC373ADB NRND

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-State

The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable input (pin LE) and an output enable input (pin OE) are common to all internal latches.

When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of pin LE.

When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications.

The 74LVC373A is functionally identical to the 74LVC573A, but has a different pin arrangement.

Not recommended for new designs (NRND), click here for the alternative product.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74LVC373ADB 74LVC373ADB,118 935218640118 SOT339-1 Order product
74LVC373ADB 74LVC373ADB,112 935218640112 SOT339-1 Order product

Features

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic
  • Wide supply voltage range from 1.2 to 3.6 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • High-impedance outputs when VCC = 0 V
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-B exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74LVC373ADB
NRND
Not for design in1.2 - 3.6TTL+/- 2438low-40~12513640.0SSOP20

Package

Type numberOrderable part number, (Ordering code (12NC))StatusMarkingPackageOutline versionReflow-/Wave solderingPacking
74LVC373ADB
NRND
74LVC373ADB,118
( 9352 186 40118 )
ActiveLVC373A
SSOP20
(SOT339-1)
SOT339-1SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1
74LVC373ADB,112
( 9352 186 40112 )
ActiveLVC373ABulk Pack

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFMSLMSL leadfree
74LVC373ADB
NRND
74LVC373ADB,11874LVC373ADB11
74LVC373ADB
NRND
74LVC373ADB,11274LVC373ADB11
Quality and reliability disclaimer

Documentation (7)

File nameTitleTypeDate
74LVC373AOctal D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateData sheet2017-07-20
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc373alvc373a IBIS modelIBIS model2013-04-07
lvclvc Spice modelSPICE model2013-05-06
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT339-1_118SSOP20; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2015-10-02
SOT339-1plastic, shrink small outline package; 20 leads; 0.65 mm pitch; 7.2 mm x 5.3 mm x 2 mm bodyOutline drawing2018-10-18

Support

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Models

File nameTitleTypeDate
lvc373alvc373a IBIS modelIBIS model2013-04-07
lvclvc Spice modelSPICE model2013-05-06

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74LVC373ADB74LVC373ADB,118935218640118Reel 13" Q1/T1Order product
74LVC373ADB74LVC373ADB,112935218640112Bulk PackOrder product

Sample

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