74LVC1G79-Q100

Single D-type flip-flop; positive-edge trigger

The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G79GV-Q100Production1.65 - 5.5CMOS/LVTTL± 322.2450low-40~12527063.3169TSOP5
74LVC1G79GW-Q100Production1.65 - 5.5CMOS/LVTTL± 322.2450low-40~12540725.0271TSSOP5

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC1G79GV-Q100
TSOP5
(SOT753)
SOT753Reel 7" Q3/T4, ReverseActiveStandard Marking74LVC1G79GV-Q100H
( 9353 065 27125 )
74LVC1G79GW-Q100
TSSOP5
(SOT353-1)
SOT353-1Reel 7" Q3/T4, ReverseActiveStandard Marking74LVC1G79GW-Q100H
( 9353 065 26125 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74LVC1G79GV-Q10074LVC1G79GV-Q100H74LVC1G79GV-Q100Always Pb-free11
74LVC1G79GW-Q10074LVC1G79GW-Q100H74LVC1G79GW-Q100Always Pb-free11
Quality and reliability disclaimer

Documentation (12)

File nameTitleTypeDate
74LVC1G79_Q100Single D-type flip-flop; positive-edge triggerData sheet2017-03-17
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc1g7974LVC1G79 IBIS modelIBIS model2014-10-20
Nexperia_document_leaflet_Logic_X2SON_packages_062018X2SON ultra-small 4, 5, 6 & 8-pin leadless packagesLeaflet2018-06-05
Nexperia_Selection_guide_2020Nexperia Selection Guide 2020Selection guide2020-01-31
SOT353-1_125TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code (12NC) ending 125Packing2017-11-16
SOT353-1_165TSSOP5; Reel pack; SMD; Q3 Reverse product orientation; Orderable part number ending, 165 or Z; Ordering code (12NC) ending 165Packing2013-05-15
SOT353-1plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm bodyOutline drawing2017-01-30
SOT753_125TSOP5; Reel pack for SMD, 7"; Q3/T4 product orientationPacking2020-02-14
MAR_SOT753MAR_SOT753 TopmarkTop marking2013-06-03
SOT753plastic, surface-mounted package; 5 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm bodyOutline drawing2018-10-18

Support

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Models

File nameTitleTypeDate
lvc1g7974LVC1G79 IBIS modelIBIS model2014-10-20

Ordering, pricing & availability

Sample

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