74AUP2G00-Q100

Low-power dual 2-input NAND gate

The 74AUP2G00-Q100 provides dual 2-input NAND function.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial power-down mode operation
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP2G00DC-Q100	Production	0.8 - 3.6	CMOS	± 1.9	8.3	70	2	ultra low	-40~125	203	34.1	113	VSSOP8

Package

Type number	Package	Package information	Reflow-/Wave soldering	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74AUP2G00DC-Q100	VSSOP8 (SOT765-1)	SOT765-1		SOT765-1_125	Active	p00	74AUP2G00DC-Q100H ( 9356 908 61125 )

Environmental information

Type number	Orderable part number	Chemical content	RoHS	RHF-indicator	Leadfree conversion date
74AUP2G00DC-Q100	74AUP2G00DC-Q100H	74AUP2G00DC-Q100			week 25, 2019

Quality and reliability disclaimer

Documentation (6)

File name	Title	Type	Date
74AUP2G00_Q100	Low-power dual 2-input NAND gate	Data sheet	2023-07-14
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup2g00	aup2g00 IBIS model	IBIS model	2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10
SOT765-1	plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body	Package information	2022-06-03

Support

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Models

File name	Title	Type	Date
aup2g00	aup2g00 IBIS model	IBIS model	2013-04-07

Ordering, pricing & availability

74AUP2G00DC-Q100

Sample

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