74AUP1T45GN

Low-power dual supply translating transceiver; 3-state

The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)) which enable bidirectional level translation. Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC(A) and VCC(B) ranges. The device ensures low static and dynamic power consumption and is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND, both A and B are in the high-impedance OFF-state.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74AUP1T45GN 74AUP1T45GN,132 935291753132 SOT1115 Order product

Features

  • Wide supply voltage range:
    • VCC(A): 1.1 V to 3.6 V
    • VCC(B): 1.1 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

Target applications

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1T45GNProduction1.1 - 3.61.1 - 3.6CMOS+/- 1.915.61ultra low-40~12529515.5183XSON6

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP1T45GN
XSON6
(SOT1115)
SOT1115Reel 7" Q1/T1, Q3/T4Activep574AUP1T45GN,132
( 9352 917 53132 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AUP1T45GN74AUP1T45GN,13274AUP1T45GNAlways Pb-free11
Quality and reliability disclaimer

Documentation (7)

File nameTitleTypeDate
74AUP1T45Low-power dual supply translating transceiver; 3-stateData sheet2017-05-03
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
Nexperia_document_guide_Logic_translators_201711Nexperia Logic TranslatorsBrochure2017-12-05
aup1t45aup1t45 IBIS modelIBIS model2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
SOT1115_132Reversed product orientation 12NC ending 132Packing2013-04-04
SOT1115plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm bodyOutline drawing2018-11-14

Support

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Models

File nameTitleTypeDate
aup1t45aup1t45 IBIS modelIBIS model2014-12-21

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74AUP1T45GN74AUP1T45GN,132935291753132Reel 7" Q1/T1, Q3/T4Order product

Sample

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