NCA9537DP

The NCA9537-Q100 is a 4-bit bidirectional I/O expander compliant with I²C and SMBus protocols, operating over a wide supply range of 1.65 V to 5.5 V. It enables remote GPIO expansion for microcontroller-based systems via a standard two- wire interface (SCL/SDA), supporting clock frequencies up to 1 MHz (Fast-Mode Plus).

Part of Nexperia’s advanced I²C-bus expander portfolio, the device is optimized for space-constrained applications requiring additional I/O such as LED control, button interfacing, sensor integration, status indication, and signal routing. Its compact form factor and low-power operation make it well-suited for consumer, industrial, and IoT designs.

The NCA9537-Q100 provides 4 bits in Configuration Register defining each I/O as input or output, 4 bits in Input Port Register capturing the logic state of input pins, 4 bits in Output Port Register controlling the output logic levels and 4 bits in Polarity Inversion Register allowing inversion of input logic (active HIGH or LOW).

The system controller configures the I/Os via the Configuration Register, accesses real-time data through the Input Port Register, and controls the outputs through the Output Port Registers. The Polarity Inversion Register allows flexible logic interpretation. All registers are accessible via the I²C interface.

The NCA9537-Q100 supports I²C General Call address (0x00), which upon receiving a specific reset command (0x06), to initiate a software-triggered reset. This is ideal for systems lacking hardware reset or requiring simultaneous reset of multiple devices.

The NCA9537-Q100 has an open-drain interrupt output (INT) which is activated when any one of the GPIO changes from its corresponding input port register state, enabling efficient real-time input monitoring for applications like button interfaces or sensor events. To recover from errors like I²C time-outs, a system controller can drive the RESET input low. This resets all registers to their default state and reinitializes the I²C/SMBus interface without requiring a power cycle.

Upon power-on reset, all registers are initialized to default states, and the internal state machine is set. The device features a fixed I²C-bus address, supporting single-device operation per bus.