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NCA9617DQ

NCA9617DQ Production

Level translating Fm+ I²C-bus repeater

The NCA9617-Q100 is a CMOS dual bidirectional buffer that provides level translation for Fast-mode Plus (Fm+) I²C-bus and SMBus applications. It supports voltage translation between a low-voltage port A operating from 0.8 V to 5.5 V and a higher-voltage port B operating from 2.2 V to 5.5 V. The device preserves all standard I²C operating modes while isolating bus capacitance and voltage domains.

Both SDA and SCL lines are buffered, allowing the connection of two I²C bus segments with up to 540 pF per segment at 1 MHz operation, or up to 4000 pF at lower frequencies. This buffering enables bus extension while maintaining signal integrity. The SDA and SCL pins are overvoltage tolerant and remain high-impedance when the device is unpowered.

Port B incorporates a static level offset architecture, whereas port A eliminates static offset. This ensures that a LOW level on port B is translated to a near 0 V LOW on port A, supporting reduced voltage swings required by low-voltage logic.

Due to the static offset implementation on port B, these pins must not be directly connected to other buffers that use static or incremental offset outputs on the same side. Port A pins of multiple NCA9617-Q100 devices may be connected together to form a common bus in star configurations. Cascaded connection of multiple devices from port A to port B is supported without cumulative offset buildup; only propagation delay must be considered.

The drivers are enabled only when VCCA exceeds 0.8 V and VCCB exceeds 2.2 V. The EN pin, referenced to VCCB, provides system-level enable control and should be toggled only while the bus is idle.

On port B, the internal LOW-level output pull-down is approximately 0.54 V, with an input threshold set approximately 90 mV lower at 0.45 V to prevent internal latching. When port B is driven LOW internally, this level is not interpreted as a valid LOW at the input stage. Port A drives a hard LOW level, and its input threshold is defined at 0.35 × VCCA to ensure reliable operation when VCCA is as low as 0.8 V.
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Product details

Features and benefits

  • 2 channel, bidirectional I²C buffer isolates capacitance and allows 540 pF on either side of the device at 1 MHz and up to 4000 pF at lower speeds

  • Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V

  • Glitch free Power sequence

  • Port A operating supply voltage range of 0.8 V to 5.5 V with normal levels

  • Port B operating supply voltage range of 2.2 V to 5.5 V with static offset level

  • 5.5 V tolerant I²C-bus and enable pins

  • 0 Hz to 1000 kHz clock frequency (the maximum system operating frequency may be less than 1000 kHz because of the delays added by the repeater)

  • Active HIGH repeater enable input referenced to VCCB

  • Open-drain input/outputs

  • Lock-free operation

  • Supports arbitration and clock stretching across the repeater

  • Accommodates Standard-mode, Fast-mode and Fast-mode Plus I²C-bus devices, SMBus (standard and high power mode), PMBus and multiple controllers

  • Powered-off high-impedance I²C-bus pins

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4 kV

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1.5 kV

  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

  • Packages offered: TSSOP8 (SOT505-3)

  • Specified from -40 °C to +85 °C

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Longevity

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Interactive data sheet

How does it work?

The interactive data sheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive data sheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

Interactive data sheet