74AUP1G3208

Low-power 3-input OR-AND gate

The 74AUP1G3208 provides the Boolean function: Y = (A + B) × C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G3208GF
NRND
Not for design in1.1 - 3.6CMOS+/- 1.97.4701ultra low-40~1252906.5145XSON6
74AUP1G3208GMProduction0.8 - 3.6CMOS± 1.97.4701ultra low-40~1252906.5145XSON6
74AUP1G3208GNProduction0.8 - 3.6CMOS± 1.97.4701ultra low-40~12527511.7171XSON6
74AUP1G3208GSProduction0.8 - 3.6CMOS± 1.97.4701ultra low-40~12527214.8177XSON6
74AUP1G3208GWProduction0.8 - 3.6CMOS± 1.97.4701ultra low-40~12526438.6153TSSOP6
74AUP1G3208GXProduction0.8 - 3.6CMOS± 1.97.4701ultra low-40~125X2SON6

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP1G3208GF
NRND

XSON6
(SOT891)
SOT891Reel 7" Q1/T1, Q3/T4Activea274AUP1G3208GF,132
( 9352 813 23132 )
74AUP1G3208GM
XSON6
(SOT886)
SOT886Reel 7" Q1/T1, Q3/T4Activea274AUP1G3208GM,132
( 9352 806 17132 )
Reel 7” Q1/T1 or Q2/T3Activea274AUP1G3208GM,115
( 9352 806 17115 )
74AUP1G3208GN
XSON6
(SOT1115)
SOT1115Reel 7" Q1/T1, Q3/T4Activea274AUP1G3208GN,132
( 9352 917 34132 )
74AUP1G3208GS
XSON6
(SOT1202)
SOT1202Reel 7" Q1/T1, Q3/T4Activea274AUP1G3208GS,132
( 9352 928 58132 )
74AUP1G3208GW
TSSOP6
(SOT363)
SOT363Reel 7" Q3/T4, ReverseActivea274AUP1G3208GW,125
( 9352 806 16125 )
74AUP1G3208GX
X2SON6
(SOT1255)
SOT1255Reel 7" Q2/T3ActiveStandard Marking74AUP1G3208GXZ
( 9353 084 66147 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74AUP1G3208GF
NRND
74AUP1G3208GF,13274AUP1G3208GFAlways Pb-free11
74AUP1G3208GM74AUP1G3208GM,13274AUP1G3208GMAlways Pb-free0.03.293.04E811
74AUP1G3208GM74AUP1G3208GM,11574AUP1G3208GMAlways Pb-free0.03.293.04E811
74AUP1G3208GN74AUP1G3208GN,13274AUP1G3208GNAlways Pb-free11
74AUP1G3208GS74AUP1G3208GS,13274AUP1G3208GSAlways Pb-free11
74AUP1G3208GW74AUP1G3208GW,12574AUP1G3208GWAlways Pb-free0.03.293.04E811
74AUP1G3208GX74AUP1G3208GXZ74AUP1G3208GXweek 25, 201911
Quality and reliability disclaimer

Documentation (19)

File nameTitleTypeDate
74AUP1G3208Low-power 3-input OR-AND gateData sheet2017-03-21
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup1g320874AUP1G3208 IBIS modelIBIS model2016-02-24
Nexperia_document_leaflet_Logic_X2SON_packages_062018X2SON ultra-small 4, 5, 6 & 8-pin leadless packagesLeaflet2018-06-05
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_document_Logic_CombinationLogic_infocard_201710Combination logic solutions cardLeaflet2017-10-16
Nexperia_Selection_guide_2020Nexperia Selection Guide 2020Selection guide2020-01-31
MAR_SOT1202MAR_SOT1202 TopmarkTop marking2013-06-03
SOT1202plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1mm x 0.35 mm bodyPackage information2020-04-21
SOT1255plastic, leadless thermal enhanced extremely thin small outline package; 6 terminals; 0.4 mm pitch; 1 mm x 0.8 mm x 0.35 mm bodyPackage information2020-04-21
MAR_SOT1115MAR_SOT1115 TopmarkTop marking2013-06-03
SOT1115plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm bodyPackage information2020-04-21
SOT891plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm bodyPackage information2020-04-21
MAR_SOT891MAR_SOT891 TopmarkTop marking2013-06-03
MAR_SOT363MAR_SOT363 TopmarkTop marking2013-06-03
SOT363plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm bodyPackage information2020-04-21
MAR_SOT886MAR_SOT886 TopmarkTop marking2013-06-03
SOT886plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm bodyPackage information2020-04-21

Support

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Models

File nameTitleTypeDate
aup1g320874AUP1G3208 IBIS modelIBIS model2016-02-24

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