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Presettable synchronous 4-bit binary up/down counter
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
For 74HC193: CMOS level
For 74HCT193: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Expandable without external logic
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
|Output drive capability (mA)
|Logic switching levels
|Power dissipation considerations
|2.0 - 6.0
|Orderable part number, (Ordering code (12NC))
|Presettable synchronous 4-bit binary up/down counter
|Pin FMEA 74HC/74HCT family
|74HC193 IBIS model
|74HC193PW Nexperia Product Reliability
|HC/T User Guide
|3D model for products with SOT403-1 package
|Nexperia package poster
|plastic, thin shrink small outline package; 16 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body
|TSSOP16; Reel pack for SMD, 13"; Q1/T1 product orientation
|TSSOP16; Reel pack; SMD, 13", Turned Q4/T2 180 deg product orientation Orderable part number ending ,128 or HP Ordering code (12NC) ending 128
|TSSOP16; Reel pack; SMD, 13"; Q1 Standard product orientation; Orderable part number ending, 623 or HL; Ordering code (12NC) ending 623
|TSSOP16; Reel pack; SMD, 13"; Q1 Standard product orientation; Orderable part number ending, 653 or HL; Ordering code (12NC) ending 653
|Footprint for wave soldering
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|Orderable part number
|Ordering code (12NC)
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The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.