74LVC2G125DP-Q100

Dual bus buffer/line driver; 3-state

The 74LVC2G125-Q100 provides a dual non-inverting buffer/line driver with 3-state output. The output enable input (pin nOE) controls the 3-state output. A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74LVC2G125DP-Q100 74LVC2G125DP-Q100H 935300915125 SOT505-2 Order product

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85  °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant input/output for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low-power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC2G125DP-Q100Production1.65 - 5.5CMOS/LVTTL+/- 321752low-40~12522021.3107TSSOP8

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC2G125DP-Q100
TSSOP8
(SOT505-2)
SOT505-2Reel 7" Q3/T4, ReverseActiveV2574LVC2G125DP-Q100H
( 9353 009 15125 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRMSLMSL leadfree
74LVC2G125DP-Q10074LVC2G125DP-Q100H74LVC2G125DP-Q100Always Pb-free123.811
Quality and reliability disclaimer

Documentation (7)

File nameTitleTypeDate
74LVC2G125_Q100Dual bus buffer/line driver; 3-stateData sheet2018-09-10
AN11009Pin FMEA for LVC familyApplication note2019-01-09
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
75017668Low voltage CMOS family - LVCBrochure2015-07-09
lvc2g12574LVC2G125 IBIS modelIBIS model2014-10-20
SOT505-2_125TSSOP8: Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or H Ordering code (12NC) ending 125Packing2013-05-02
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyOutline drawing2018-11-14

Support

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Models

File nameTitleTypeDate
lvc2g12574LVC2G125 IBIS modelIBIS model2014-10-20

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74LVC2G125DP-Q10074LVC2G125DP-Q100H935300915125Reel 7" Q3/T4, ReverseOrder product

Sample

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