74AUP1G175GW-Q100

Low-power D-type flip-flop with reset; positive-edge trigger

The 74AUP1G175-Q100 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 Class 3A exceeds 5000 V
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G175GW-Q100Production1.1 - 3.6CMOS+/- 1.97.470ultra low-40~12526438.6153TSSOP6

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP1G175GW-Q100
TSSOP6
(SOT363)
SOT363Reel 7" Q3/T4, ReverseActiveaT74AUP1G175GW-Q100H
( 9353 005 11125 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AUP1G175GW-Q10074AUP1G175GW-Q100H74AUP1G175GW-Q100Always Pb-free11
Quality and reliability disclaimer

Documentation (7)

File nameTitleTypeDate
74AUP1G175_Q100Low-power D-type flip-flop with reset; positive-edge triggerData sheet2017-03-10
AN11052Pin FMEA for AUP familyApplication note2011-05-06
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
aup1g175aup1g175 IBIS modelIBIS model2014-12-21
aup1g1774AUP1G17 IBIS modelIBIS model2018-05-25
SOT363_125Tape reel SMD; reversed product orientation 12NC ending 125Packing2012-11-20
SOT363plastic, surface-mounted package; 6 leads; 1.3 mm pitch; 2 mm x 1.25 mm x 0.95 mm bodyOutline drawing2018-02-23

Support

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Models

File nameTitleTypeDate
aup1g175aup1g175 IBIS modelIBIS model2014-12-21
aup1g1774AUP1G17 IBIS modelIBIS model2018-05-25

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