74AUP2G241

Low-power dual buffer/line driver; 3-state

The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This device has an input-disable feature, which allows floating input signals. The input 1A is disabled when the output enable input 1OE is HIGH. The input 2A is disabled when the output enable input 2OE is LOW.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • Input-disable feature allows floating input conditions
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP2G241DCProduction0.8 - 3.6CMOS± 1.9702ultra low-40~12520334.1113VSSOP8
74AUP2G241GNProduction0.8 - 3.6CMOS± 1.9702ultra low-40~12523810.6148XSON8
74AUP2G241GSProduction0.8 - 3.6CMOS± 1.9702ultra low-40~12527610.8146XSON8
74AUP2G241GTProduction0.8 - 3.6CMOS± 1.9702ultra low-40~1253276.1157XSON8

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AUP2G241DC
VSSOP8
(SOT765-1)
SOT765-1Reel 7" Q3/T4, ReverseActivep4174AUP2G241DC,125
( 9352 807 38125 )
74AUP2G241GN
XSON8
(SOT1116)
SOT1116Reel 7” Q1/T1 or Q2/T3Activep174AUP2G241GN,115
( 9352 922 25115 )
74AUP2G241GS
XSON8
(SOT1203)
SOT1203Reel 7” Q1/T1 or Q2/T3Activep174AUP2G241GS,115
( 9352 927 85115 )
74AUP2G241GT
XSON8
(SOT833-1)
SOT833-1Reel 7” Q1/T1 or Q2/T3Activep4174AUP2G241GT,115
( 9352 807 39115 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74AUP2G241DC74AUP2G241DC,12574AUP2G241DCAlways Pb-free0.03.293.04E811
74AUP2G241GN74AUP2G241GN,11574AUP2G241GNAlways Pb-free11
74AUP2G241GS74AUP2G241GS,11574AUP2G241GSAlways Pb-free11
74AUP2G241GT74AUP2G241GT,11574AUP2G241GTAlways Pb-free0.03.293.04E811
Quality and reliability disclaimer

Documentation (13)

File nameTitleTypeDate
74AUP2G241Low-power dual buffer/line driver; 3-stateData sheet2019-03-21
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup2g241aup2g241 IBIS modelIBIS model2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_Selection_guide_2020Nexperia Selection Guide 2020Selection guide2020-01-31
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyPackage information2020-04-21
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2020-04-21
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2020-04-21
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyPackage information2020-04-21

Support

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Models

File nameTitleTypeDate
aup2g241aup2g241 IBIS modelIBIS model2013-04-07

Ordering, pricing & availability

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